• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.451-458
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• 2013

This paper describes a design of LIN MCU using efficient memory accessing architecture which provides concurrent data and address fetch for faster communication. By using slew rate control it can reduce EMI emission while satisfying required communication specifications. To verify the efficiency of the LIN MCU, we developed a SoC and tested for several data packets. Measurements show that this LIN MCU improves network efficiency up to 17.19 % and response time up to 31.26 % for nominal cases. EMI radiation also can be reduced up to 10 dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12B
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• pp.1733-1740
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• 2001

A monolithic 5 GHz image reject mixer using a 0.5-m GaAs MESFET technology is designed and simulated. The Mixer exhibits a 13.56 dB down-conversion gain, a SSB (Single SideBand) noise figure of 11.91 dB, an input IP3 (third order intercept point) of -3.73 dBm and a PldB (1-dB compression point) of -11.0 dBm. The critical issue in the image reject mixer is the phase accuracy and magnitude balance of the 90 phase shifting network. The proposed image reject mixer realizes a 90 phase shifter on chip. This phase shifting network does not need any phase adjusting to achieve the phase error specification of 3 over a frequency range from 800 MHz to 1GHz. The simulated overall image rejection ratio is better than 50 dB.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.2
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• pp.45-49
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• 2014

In this work, a phase shifter radio-frequency integrated chip (RFIC) using a simple all-pass network is presented. As a tuning element of the phase shifter RFIC, tunable capacitors with a multi-layer dielectric of a para-/ferro-/para-electrics using a high tunable BST ferroelectric and a low-loss BZN paraelectric thin film were utilized. In order to evaluate and analyze the fabricated phase shifter RFIC, the same elements such as an inductor and capacitor integrated into it are also fabricated and tested. The designed phase shifter RFIC was fabricated on a quartz substrate in the size of $1.16{\times}1.21mm^2$. As the test results, the maximum phase difference of $350^{\circ}$ is obtained at 15 V and its tuning frequency bandwidth is 90 MHz from 2.72 to 2.81GHz.

• Annual Conference of KIPS
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• 2002.11b
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• pp.1281-1284
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• 2002

본 논문은 인터넷을 이용한 음성통신 서비스를 제공하기 위해 사용되는 VoIP 시스템 칩 설계 및 기능 검증을 위한 보드 개발에 관한 것이다. 구성이 간단한 시스템을 구현하기 위하여 32 비트 RISC 프로세서인 ARM922T 프로세서 코어를 중심으로 IP 망 접속 기능, 톤 발생 및 음성신호 접속기능과 다양한 사용자 정합 기능을 가지는 VoIP 시스템 칩을 설계하고, 이 칩의 기능을 검증하기 위하여 시험 프로그램 및 통신 프로토콜을 개발하였으며, 각종 설계 및 시뮬레이션 툴을 사용하고 ARM922T와 FPGA가 결합된 Excalibur를 사용한 시험용 보드를 개발하여 시험하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.43-49
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• 2015

In this paper, we propose enhanced wireless power transfer system based on magnetic resonance for portable electronic device charging. Resonators were designed and fabricated for efficiency improvement and miniaturization through electromagnetism simulation using HFSS(High Frequency Structure Simulator). Impedance matching network is employed to minimize reflections that is caused by difference between input impedance and output impedance. Receiver IC that consist of rectifier and Low Drop Out(LDO) regulator were designed and fabricated to reduce power loss. This chip is implemented in $0.35{\mu}m$ BCD technology. A maximum overall efficiency of 73.8% is determined for the system through experimental verification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.14-24
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• 2002

In this paper, a design of the pulsewidth-modulation(PWM) neural network with both retrieving and learning function is proposed. In the designed PWM neural system, the input and output signals of the neural network are represented by PWM signals. In neural network, the multiplication is one of the most commonly used operations. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits. Thus, the designed neural network only occupies the small chip area. By applying some circuit design techniques to reduce the nonideal effects, the designed circuits have good linearity and large dynamic range. Moreover, the delta learning rule can easily be realized. To demonstrate the learning capability of the realized PWM neural network, the delta learning nile is realized. The circuit with one neuron, three synapses, and the associated learning circuits has been designed. The HSPICE simulation results on the two learning examples on AND function and OR function have successfully verified the function correctness and performance of the designed neural network.

• The Journal of the Korea Contents Association
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• v.9 no.11
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• pp.90-99
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• 2009

This paper presents the implementation of RFID EPC global network educational system based on using 900MHz air interface between the reader and the active tag. The software of reader and the active tag is developed on embedded environment, and the software of PC controlling the reader is based on window OS operated as the server. The ATmega128 VLSI chip is used for the processor of the reader and the active tag. As the development environment, AVR compiler is used for the reader and the active tag of which the programming language is C. The visual C++language of the visual studio on the PC activated as the server is used for development language. Main functions of this system are to control tag containing EPC global Data by PC through the reader, to obtain information of tag through the internet and to read/write data on tag memory. Finally the data written from the active tag's memory is sent to the PC via the reader as "read" operation and compare the received data with one already sent to the tag. Software implementation of 900MHz EPC global RFID educational system is done on the basis of these functions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.23-32
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• 2006

Fast and accurate power bus design (FAPUD) method for multi-layers high-speed digital boards is devised for the power supply network design tool for accurate and precise high speed board. FAPUD is constructed, based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching can be carried out because the I/O switching effect on a power supply noise can be estimated over the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1510-1516
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• 2011

As emergence of the ubiquitous society, it is possible to access the network for services needed to us in anytime and anywhere. The phenomena has been accelerated by revitalization of the sensor network offering the sensing information and data. Currently, sensor network contributes the convenience for various services such as environment monitoring, health care and home automation. However, sensor network has a weak point compared to traditional network, which is easily exposed to attacker. For this reason, messages communicated over the sensor network, are encrypted with symmetric key and transmitted. A number of symmetric cryptography algorithms have been researched. Among of them HIGHT algorithm in hardware and software implementation are more efficient than tradition AES in terms of speed and chip size. Therefore, it is suitable to resource constrained devices including RFID tag, Sensor node and Smart card. In the paper, we present the optimized software implementation on the ultra-light symmetric cryptography algorithm, HIGHT.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.6
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• pp.44-55
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• 2009

Diagnosis of diseases using gene expression data obtained from microarray chip is an active research area recently. It has been done by general machine learning algorithms, because it is difficult to analyze directly. However, recent research results about the analysis based on the interaction between genes is essential for the gene expression analysis, which means the analysis using the traditional machine learning algorithms has limitations. In this paper, we classify the gene expression data using the hyper-network model that considers the higher-order correlations between the features, and then compares the classification accuracies. And also, we present the new hypo-network model that improve the disadvantage of existing model, and compare the processing performances of the existing hypo-network model based on general sequential processor and the improved hypo-network model implemented on parallel processors. In the experimental results, we show that the performance of our model shows improved and competitive classification performance than traditional machine learning methods, as well as, the existing hypo-network model. We show that the performance is maximized when the hypernetwork model is implemented on our parallel processors.