• IE interfaces
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• v.11 no.3
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• pp.77-87
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• 1998

Intelligent Peripheral(IP) system is to provide specialized resource functions (SRF) such as playing announcement, collecting user information, and receiving messages in the Advanced Intelligent Network (AIN). We analyze the call processing capacity of an AIN IP system being developed in ETRI through an extensive simulation using SLAM II under a variety of AIN service scenarios. We consider televoting (VOT) and universal personal telecommunication (UPT) services which are to be provided at the fit implementation of the AIN in Korea. As the performance criteria to determine the call processing capacity, processor utilization, delay and call loss probability are considered. It turns out that the major processor called SAMP is the bottleneck processor, the service response delay dominates the delay performance, and the call loss probability becomes the primary criterion in determining the call processing capacity of the AIN IP system. It is also shown that the call processing capacity of the AIN IP system is determined by the utilization of the processor and the delay performance when the VOT ratio is below 70 percent but it is determined by the call loss probability due to the lack of service channels for providing the SRF operations.

• Journal of Semiconductor Engineering
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• v.2 no.2
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• pp.130-135
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• 2021

Recently, deep neural networks (DNNs) are actively used for action control so that an autonomous system, such as the robot, can perform human-like behaviors and operations. Unlike recognition tasks, the real-time operation is essential in action control, and it is too slow to use remote learning on a server communicating through a network. New learning techniques, such as reinforcement learning (RL), are needed to determine and select the correct robot behavior locally. In this paper, we propose an energy-efficient DNN processor with a LUT-based processing engine and near-zero skipper. A CNN-based facial emotion recognition and an RNN-based emotional dialogue generation model is integrated for natural HRI system and tested with the proposed processor. It supports 1b to 16b variable weight bit precision with and 57.6% and 28.5% lower energy consumption than conventional MAC arithmetic units for 1b and 16b weight precision. Also, the near-zero skipper reduces 36% of MAC operation and consumes 28% lower energy consumption for facial emotion recognition tasks. Implemented in 65nm CMOS process, the proposed processor occupies 1784×1784 um2 areas and dissipates 0.28 mW and 34.4 mW at 1fps and 30fps facial emotion recognition tasks.

• The KIPS Transactions:PartC
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• v.16C no.4
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• pp.417-422
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• 2009

Implementation of DPI(Deep Packet Inspection) system on a general purpose multiprocessor platform is an attractive option from the implementation cost point of view, since it does not require high-cost customized hardware. Load balancing has been considered as a primary means to achieve high performance in multi processor systems. We claim, however, that in case of DPI system design simply balancing the load of each processor does not necessarily yield the highest system performance. Instead, we propose a method in which tasks are allocated to processors based on their functions. We implemented the proposed method in dual processor Linux system and compare its performance with the existing load balancing methods. Under the proposed method, one processor is dedicated to deal with interrupt handling and generic packet processing, while another processor is dedicated to DPI processing. According to experimental results, the proposed scheme outperforms the existing schemes by 60%, mainly because of the reduction of cache miss and spin lock occurrences.

• Journal of Institute of Control, Robotics and Systems
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• v.3 no.5
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• pp.542-554
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• 1997

In this paper, we present a resource conscious approach to designing distributed real-time systems as an extension of our original approach [8][9] which was limited to single processor systems. Starting from a given task graph and a set of end-to-end constraints, we automatically generate task attributes (e.g., periods and deadlines) such that (i) the task set is schedulable, and (ii) the end-to-end timing constraints are satisfied. The method works by first transforming the end-to-end timing constraints into a set of intermediate constraints on task attributes, and then solving the intermediate constraints. The complexity of constraint solving is tackled by reducing the problem into relatively tractable parts, and then solving each sub-problem using heuristics to enhance schedulability. In this paper, we build on our single processor solution and show how it can be extended for distributed systems. The extension to distributed systems reveals many interesting sub-problems, solutions to which are presented in this paper. The main challenges arise from end-to-end propagation delay constraints, and therefore this paper focuses on our solutions for such constraints. We begin with extending our communication scheme to provide tight delay bounds across a network, while hiding the low-level details of network communication. We also develop an algorithm to decompose end-to-end bounds into local bounds on each processor of making extensive use of relative load on each processor. This results in significant decoupling of constraints on each processor, without losing its capability to find a schedulable solution. Finally, we show, how each of these parts fit into our overall methodology, using our previous results for single processor systems.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.5 s.335
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• pp.23-28
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• 2005

Recently, new concept, NP(Network Processor) was emerged into communication systems to cope with the various service requirements from Internet users. NP is an unique promising technique to capable of implementing of the packet processing in wire-speed and providing the flexibility for supporting the newly network services, having satisfied with implementation using hardware and software respectively in past, This paper deals with the implementation techniques and evaluation results of the line card capable to do packet forwarding function with packet processing power of wire-speed and applicable to various physical interfaces. There are several interfaces of POS, Gigabit ethernet and EPON in E-OLT(EPON Optical Line Terminal) system of PATH(Photonic Access To Home) network. Therefore, the E-OLT's packet forwarding engine have to support various subscriber's interface in wire speed. Our system is implemented the subscriber's card in daughter board and the setup procedure is done by system firmware based on the module's identifier acquired from installed physical board.

• Journal of Broadcast Engineering
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• v.10 no.1 s.26
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• pp.83-102
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• 2005

The problem of video scheduling is analyzed in the framework of divisible load scheduling. A divisible load can be divided into any number of fractions (parts) and can be processed/computed independently on the processors in a distributed computing system/network, as there are no precedence relationships. In the video scheduling, a frame can be split into any number of fractions (tiles) and can be processed independently on the processors in the network, and then the results are collected to recompose the single processed frame. The divisible load arrives at one of the processors in the network (root processor) and the results of the computation are collected and stored in the same processor. In this problem communication delay plays an important role. Communication delay is the time to send/distribute the load fractions to other processors in the network. and the time to collect the results of computation from other processors by the root processors. The objective in this scheduling problem is that of obtaining the load fractions assigned to each processor in the network such that the processing time of the entire load is a minimum. We derive closed-form expression for the processing time by taking Into consideration the communication delay in the load distribution process and the communication delay In the result collection process. Using this closed-form expression, we also obtain the optimal number of processors that are required to solve this scheduling problem. This scheduling problem is formulated as a linear pro-gramming problem and its solution using neural network is also presented. Numerical examples are presented for ease of understanding.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.440-443
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• 2001

As inter-network traffics grows rapidly, the router systems as a network component becomes to be capable of not only wire-speed packet processing but also plentiful programmability for quality services. A network processor technology is widely used to achieve such capabilities in the high-end router. Although providing two such capabilities, the network processor can't support a deep packet processing at nominal wire-speed. Considering QoS may result in performance degradation of processing packet. In order to achieve foster processing, one chipset of network processor is occasionally not enough. Using more than one urges to consider a problem that is, for instance, an out-of-order delivery of packets. This problem can be serious in some applications such as voice over IP and video services, which assume that packets arrive in order. It is required to develop an effective packet processing mechanism leer using more than one network processors in parallel in one linecard unit of the router system. Simulation analysis is also needed for verifying the mechanism. We propose the packet processing mechanism consisting of more than two NPs in parallel. In this mechanism, we use a load-balancing algorithm that distributes the packet traffic load evenly and keeps the sequence, and then verify the algorithm with simulation analysis. As a simulation tool, we use DEVSim++, which is a DEVS formalism-based hierarchical discrete-event simulation environment developed by KAIST. In this paper, we are going to show not only applicability of the DEVS formalism to hardware modeling and simulation but also predictability of performance of the load balancer when implemented with FPGA.

• ETRI Journal
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• v.29 no.3
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• pp.371-380
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• 2007

This paper proposes a new automatic compensation network (ACN) for a system-on-chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on-chip ACN using 0.18 ${\mu}m$ SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design-for-testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.

• Journal of Sensor Science and Technology
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• v.18 no.5
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• pp.337-342
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• 2009

This paper describes a robust mobile u-healthcare system with multiple physiological signs measurement capability in real time with integration of WSN(wireless sensor network) technology and CDMA(code division multiple access) network. A cellular phone receives health data in WSN and performs local physiological signs analysis at a phone processor, and then transmits abnormal data to server for further detail or precise health signal evaluation by a medical doctor over a CDMA network. Physiological signs of the patients are continuously monitored, processed and analyzed locally at cellular phone process to produce useful medical information for diagnosis and tracking purposes. By local simple analysis in cellular phone processor we can save the data transmission cost in CDMA network. By using the developed integrate ubiquitous healthcare service architecture, patients can realize self-health checking so that the prevention actions can be taken earlier. Appropriate self-monitoring and self-management can cure disease and relieve pain especially for patients who suffer from chronic diseases that need long term observation.