• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(1)
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• pp.359-362
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• 2002

In this paper, we propose a structure of 800bps high speed router and a gigabit Ethernet line interface board. Having Programmability, network processor is applied to gjgabit Ethernet line interface board. Also, we propose a new method to upgrade image files that consist of operating system and drivers. It is possible to upgrade image files for several boards at once and to reduce the elapsed time for image upgrade using tile proposed method.

• 정보학연구
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• 제10권3호
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.

• 전자통신동향분석
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• 제32권6호
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• pp.57-65
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• 2017

Neural network based AI computing is a promising technology that reflects the recognition and decision operation of human beings. Early AI computing processors were composed of GPUs and CPUs; however, the dramatic increment of a floating point operation requires an energy efficient AI processor with a highly parallelized architecture. In this paper, we analyze the trends in processor architectures for AI computing. Some architectures are still composed using GPUs. However, they reduce the size of each processing unit by allowing a half precision operation, and raise the processing unit density. Other architectures concentrate on matrix multiplication, and require the construction of dedicated hardware for a fast vector operation. Finally, we propose our own inAB processor architecture and introduce domestic cutting-edge processor design capabilities.

• 정보처리학회논문지:소프트웨어 및 데이터공학
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• 제2권2호
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• pp.131-136
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• 2013

멀티코어 프로세서는 다수의 컴퓨팅 코어를 제공해줌으로써 응용 프로세스들의 병렬성을 증대시키고 전체 시스템의 처리율을 크게 향상시켜주고 있다. 최근 멀티코어의 구조적인 특징에 의해서 프로세서 친화도에 따른 네트워크 I/O 성능 차이를 관찰하고, 많은 연구자들이 최적의 프로세서 친화도를 결정하기 위한 연구를 진행하고 있다. 기존의 동적 프로세서 친화도 결정 기법은 응용 프로그램의 수정과 시스템 사양 변경에 투명하게 대처할 수 있으나, 각 응용 프로그램의 고유 특성과 경험을 통해서 수집할 수 있는 정보를 충분히 얻을 수 없다는 제한사항이 있다. 따라서 최적의 프로세서 친화도를 제공하기 어렵다. 본 연구는 프로세서 친화도 결정을 위해서 의미 있는 시스템 변수를 획득하고 최적의 친화도 결정을 지원하기 위한 도구를 제안한다. 구현된 도구는 동적 친화도 결정에 활용되어 그 한계를 극복하고 더 높은 네트워크 대역폭을 제공할 수 있음을 보인다.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 1994년도 추계학술발표회 및 정기총회
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• pp.32-32
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• 1994

In this example, a message passing based multicomputer system with general interdonnedtion network is considered. After multicomputer systems are developed with morm-hole routing network, topologies of interconecting network are not major considertion for process management and resource sharing. Tehre is an independeent operating system kernel oneach node. It communicates with other kernels using message passingmechanism. Based on this architecture, the problem is how mech does performance degradation will occur in the case of processor sharing on multicomputer systems. Processor sharing between application programs is veryimprotant decision on system performance. In almost cases, application programs running on massively parallel computer systems are not so much user-interactive. Thus, the main performance index is system throughput. Each application program has various communication patterns. and the sharing of processors causes serious performance degradation in hte worst case such that one processor is shared by two processes and another processes are waiting the messages from those processes. As a result, considering this problem is improtant since it gives the reason whether the system allows processor sharingor not. Input data has many parameters in this simulation . It contains the number of threads per task , communication patterns between threads, data generation and also defects in random inupt data. Many parallel aplication programs has its specific communication patterns, and there are computation and communication phases. Therefore, this phase informatin cannot be obtained random input data. If we get trace data from some real applications. we can simulate the problem more realistic . On the other hand, simualtion results will be waseteful unless sufficient trace data with varisous communication patterns is gathered. In this project , random input data are used for simulation . Only controllable data are the number of threads of each task and mapping strategy. First, each task runs independently. After that , each task shres one and more processors with other tasks. As more processors are shared , there will be performance degradation . Form this degradation rate , we can know the overhead of processor sharing . Process scheduling policy can affects the results of simulation . For process scheduling, priority queue and FIFO queue are implemented to support round-robin scheduling and priority scheduling.

• 전자공학회논문지B
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• 제30B권2호
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• pp.44-50
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• 1993

In this paper, we will present an array processor for implementation of digital neural networks. Back-propagation model can be formulated as a consecutive matrix-vector multiplication problem with some prespecified thresholding operation. This operation procedure is suited for the design of an array processor, because it can be recursively and repeatedly executed. Systolic array circuit architecture with Residue Number System is suggested to realize the efficient arithmetic circuit for matrix-vector multiplication and compute sigmoid function. The proposed design method would expect to adopt for the application field of neural networks, because it can be realized to currently developed VLSI technology.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.624-627
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• 1988

This paper describes the implementation of recognition of speaker - dependent Korean spoken continuous digits. The recognition system can be divided into two parts, acoustic - phonetic processor and lexical decoder. Acoustic - phonetic processor calculates the feature vectors from input speech signal and the performs frame labelling and phone labelling. Frame labelling is performed by Bayesian classification method and phone labelling is performed using labelled frame and posteriori probability. The lexical decoder accepts segments (phones) from acoustic - phonetic processor and decodes its lexical structure through phone network which is constructed from phonetic representation of ten digits. The experiment carried out with two sets of 4continuous digits, each set is composed of 35 patterns. An evaluation of the system yielded a pattern accuracy of about 80 percent resulting from a word accuracy of about 95 percent.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2009년도 춘계학술대회 논문집
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• pp.731-734
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• 2009

KIER has been developed a compact and highly efficient fuel processor which is one of the key component of the residential PEM fuel cells system. The fuel processor uses methane steam reforming to convert natural gas to a mixture of water, hydrogen, carbon dioxide, carbon monoxide and unreacted methane. Then carbon monoxide is converted to carbon dioxide in water-gas-shift reactor and preferential oxidation reactor. A start-up time of the fuel processor is about 1h and CO concentration among the final product is maintained less than 5 vol. ppm. To achieve high thermal efficiency of 80% on a LHV basis, an optimal thermal network was designed. Internal heat exchange of the fuel processor is so efficient that the temperature of the reformed gas and the flue gas at the exit of the fuel processor remains less than $100^{\circ}C$. A compact design considering a mixing and distribution of the feed was applied to reduce the reactor volume. The current volume of the fuel processor is 17L with insulation.

• 한국지능시스템학회논문지
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• 제16권4호
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• pp.485-492
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• 2006

본 논문은 휴머노이드 로봇 ISHURO의 분산 제어를 위한 네트웍 구현에 대해 다루고 있다. 일반적으로 휴머노이드형 로봇은 기구학적으로 유연한 동작을 위해 다수의 자유도가 필요하다. 이를 구현하기 위해서는 중앙에서 일괄적으로 처리 하는 것 보다 간결 하면서도 유연성을 줄 수 있는 분산 처리 방법이 선호되고 있다. 분산 처리를 위한 제어기를 구성할 때는 로봇의 모터를 독립적으로 제어하기 위한 제어기가 별도로 필요하며 모듈 간에는 정해진 시간 내에 데이터를 교환할 수 있는 통신 기법이 필요하다. ISHURO의 각 관절은 자체 내에 독립된 DSP를 내장하고 있으며 CAN 네트웍을 이용하여 모듈간의 통신을 하여 구동기를 재어하거나 센서의 값을 모니터링 할 수 있게 되어 있다. 본 논문에서는 이를 위한 통신 구조를 제안하고 필요한 전송 메시지를 정의하고, 전송시간을 분석하여 로봇 분산 제어기 구조에 적절한 전송 프로토콜을 제시하였다. 모든 과정은 Matlab을 이용하여 컴퓨터모의실험을 수행하였고 실제 휴머노이드 로봇에 적용하여 보행실험을 통해 검증 하였다.

• 대한전자공학회논문지SD
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• 제42권2호
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• pp.89-96
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• 2005

본 논문은 ATM 망에서 멀티미디어 데이터 서비스를 지원하기 위한 가입자단 플랫폼을 제안한다. AAL2 프로토콜, 스케줄러 알고리듬 등이 별도의 AAL2 프로세서로 설계되어 제안된 플랫폼은 AAL/ATM 관련 기능이 소프트웨어로 처리되던 기존 플랫폼에 비해 호스트 프로세서의 부하를 크게 줄일 수 있으며 ATM망을 통한 멀티미디어 데이터의 실시간 처리가 용이하게 하였다. 2중 타임 슬롯 링 구조를 적용한 ATS(Adaptive Time Slot) 스케쥴러는 VBR-rt, UBR, CBR 트래픽의 데이터 스케쥴링을 위한 효과적이고 간단한 방안을 제공한다 음성 압축 및 처리를 위하여 TI의 TMS320C5402 DSP를 적용하였고 AAL2 프로세서는 0.35 마이크론 공정에서 칩으로 제작되었다. VoDSL(Voice over DSL) 서비스를 위한 프로토콜을 구현하여 가입자 단말을 설계 제작하고 시험망에서 실험을 해 본 결과 $97\%$이상의 통화 성공율과 안정된 음성 서비스를 보장할 수 있음을 알 수 있다.