• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.571-573
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• 2002

네트워크 관련 기술들이 테라급으로 급속히 발전하고 있는데 비해, 상대적으로 네트워크의 발전 속도에 뒤지고 있는 네트워크 침입 탐지 시스템의 성능 향상을 위해서, 기존의 소프트웨어 방식으로 구현된 침입 탐지 시스템을 고속의 패킷 처리에 뛰어난 성능을 가지고 있는 네트워크 프로세서를 이용하여 재설계 및 구현하였다. 네트워크 침입 탐지 시스템에서 대부분의 수행시간을 차지하는 네트워크 패킷을 분류하고, 이상 패킷을 탐지하는 기능을 인텔의 IXP1200 네트워크 프로세서의 마이크로엔진이 고속으로 패킷을 처리하게 함으로써 네트워크 침입 탐지 시스템의 성능 향상을 도모하였다.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.533-536
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• 1998

The intent of this paper is to describe a neural network structure called dynamic neural processor(DNP), and examine how it can be used in developing a learning scheme for computing robot inverse kinematic transformations. The architecture and learning algorithm of the proposed dynamic neural network structure, the DNP, are described. Computer simulations are provided to demonstrate the effectiveness of the proposed learning using the DNP.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.10
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• pp.2059-2063
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• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.4
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• pp.447-454
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• 2003

The forwarding enging, which handles the incoming frames and forwards them to the appropriate outgoing interface, is the crucial factor of the router´s performance. As the MPLS label edge router provides the facility that it is capable of interworking with various kinds of networks, the forwarding engine should have the flexibility processing the corresponding types of frames from such network interfaces. In order to support the flexibility, we implement the forwarding engine for the MPLS LER with ATM interfaces based on the programmable Ethernet packet processor. By exploiting instinct loop-back functionality of Ethernet packet processor, our forwarding engine handles and forwards the frames from/to ATM interfaces. The performance of our forwarding engine is evaluated by experiments on the effect of looping frames back and the number of Ethernet packet processor´s instructions.

• Korean Chemical Engineering Research
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• v.52 no.6
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• pp.720-726
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• 2014

PEM fuel cell vehicles have been getting much attraction due to a sort of highly clean and effective transportation. The onboard fuel processor, however, is inevitably required to supply the hydrogen by conversion from some fuels since there are not enough available hydrogen stations nearby. A lot of studies have been focused on analyses of ATR reactor under the assumption of thermo-neutral condition and those of the optimized process for the minimization of energy consumption using thermal efficiency as an objective function, which doesn't guarantee the maximum hydrogen production. In this study, the analysis of optimization for 100 kW PEMFC onboard fuel processor was conducted targeting various fuels such as gasoline, LPG, diesel using newly defined hydrogen efficiency and keeping simply synthesized heat exchanger network regardless of external utilities leading to compactness and integration. Optimal result of gasoline case shows 9.43% reduction compared to previous study, which shows the newly defined objective function leads to better performance than thermal efficiency in terms of hydrogen production. The sensitivity analysis was also done for hydrogen efficiency, heat recovery of each heat exchanger, and the cost of each fuel. Finally, LPG was estimated as the most economical fuel in Korean market.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.48-58
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• 2006

This paper presents 8x8 two dimensional DCT/IDCT processor of adder-based distributed arithmetic architecture without applying ROM units in conventional memories. To reduce hardware cost in the coefficient matrix of DCT and IDCT, an odd part of the coefficient matrix was shared. The proposed architecture uses only 29 adders to compute coefficient operation in the 2-D DCT/IDCT processor, while 1-D DCT processor consists of 18 adders to compute coefficient operation. This architecture reduced 48.6% more than the number of adders in 8x8 1-D DCT NEDA architecture. Also, this paper proposed a form of new transpose network which is different from the conventional transpose memory block. The proposed transpose network block uses 64 registers with reduction of 18% more than the number of transistors in conventional memory architecture. Also, to improve throughput, eight input data receive eight pixels in every clock cycle and accordingly eight pixels are produced at the outputs.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.5
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• pp.257-266
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• 2006

Recently TCP/IP Offload Engine (TOE) technology, which processes TCP/IP on a network adapter instead of the host CPU, has become an important approach to reduce TCP/IP processing overhead in the host CPU. There have been two approaches to implementing TOE: software TOE, in which TCP/IP is processed by an embedded processor on a network adapter; and hardware TOE, in which all TCP/IP functions are implemented by hardware. This paper proposes a hybrid TOE that combines software and hardware functions in the TOE. In the hybrid TOE, functions that cannot have guaranteed performance on an embedded processor because of heavy load are implemented by hardware. Other functions that do not impose as much load are implemented by software on embedded processors. The hybrid TOE guarantees network performance near that of hardware TOE and it has the advantage of flexibility, because it is easy to add new functions or offload upper-level protocols of TCP/IP. In this paper, we developed a prototype board with an FPGA and an ARM processor to implement a hybrid TOE prototype. We implemented the hardware modules on the FPGA and the software modules on the ARM processor. We also developed a coprocessing mechanism between the hardware and software modules. Experimental results proved that the hybrid TOE prototype can greatly reduce the load on a host CPU and we analyzed the effects of the coprocessing mechanism. Finally, we analyzed important features that are required to implement a complete hybrid TOE and we predict its performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.31-38
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• 2008

This paper describes sensor network system implementation for the IEEE 1451.2 standard which guarantees compatibilities between various wired sensors. The proposed system consists of the Network Capable Application Processor(NCAP) in the IEEE 1451.0, the Transducer Independent Interface(TII) in the IEEE 1451.2, the Transducer Electronic Data Sheet(TEDS) and sensors. The research goal of this study is to minimize and optimize system complexity for IC design. The NCAP is implemented using C language in personal computer environment. TII is used in the parallel port between PC and an FPGA application board. Transducer is implemented using Verilog on the FPGA application board. We verified the proposed system architecture based on the standards.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.181-183
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• 2001

인터넷에서 저성능의 소프트웨어적인 처리 또는 고성능의 하드웨어 처리를 하는 장비의 단점을 보완하기 위해서 네트웍프로세서를 사용하는 방법이 등장하였다. 네트웍프로세서를 이용해서 네트웍기능을 지원하기 위해서는 한정된 자원을 효율적으로 활용하기 위해서 스케줄러가 요구된다. 네트웍프로세서에서 스케줄러를 설계하기 위해서 필요한 사항과 구조등에 관해서 알아본다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.258-262
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• 2004

Storage over Ethernet (SoE) is a network storage architecture that allows direct attachment of existing ATA/ATAPI devices to Ethernet without a separate server. Unlike SAN, no server computer intervenes between the storage and the client hosts. We propose a SoE disk controller (SoEDC) amenable to low-cost, single-chip implementation that processes a simplified L3/L4 protocol and converts commands between Ethernet and ATA/ATAPI, while the rest of the complex tasks are performed by the remote hosts. Thanks to simple architecture and protocol, the SoEDC implemented on a single $4mm{\times}4mm$ chip in 0.18um CMOS technology achieves maximum throughput of 55MB/s on Gigabit Ethernet, which is comparable to that of a high-performance disk storage locally attached to a host computer.