• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.6
• /
• pp.1045-1054
• /
• 2006

In this paper, described a design result of bus interface modulo for multiple level MU-SID-1553 data bus network. In general, MIL-SID-1553 network is used for single level data bus topology. But, according to applied system's structure. multiple level bus architecture is required., And for his, micro processor must be involved for system be, and a additional hardware and software functions are needed. The designed data bus interface module is simply consists of communication transceivers and simple electronic circuit without micro processor. Through the hardware testing and software simulation, the functional performance of the designed interface module was successfully validated.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2012.04a
• /
• pp.514-517
• /
• 2012

최근 인터넷 사용자 증가와 네트워크를 기반의 응용 프로그램이 다양하게 개발되고 있다. 또한 스마트 폰과 매블릿 PC 의 대중화로 누구나 쉽게 인터넷을 통해 정보검색 서비스를 이용할 수 있다. 따라서 갈수록 증가하는 패킷에 대한 제]어와 이동, 삭제 등과 같은 처리를 빠르게 하기 위해 네트워크 프로세서 (Network Processor)가 개발되었다. 네트워크 프로세서는 패킷 제어와 이동, 삭제를 수행하는데 최적화되어 있다. 하지만 네트워크 프로세서를 개발한 회사마다 교차개발환경 툴과 개발언어가 서로 다르기 때문에 소스코드 재사용 및 확장이 어렵다. 또한 네트워크 프로세서에서 동작하는 프로그램을 매스트 하기 위해 하드웨어 장비가 필요하고 네트워크 프로세서에 종속적인 개발환경과 언어를 배우는 것은 프로그래머에게 큰 부담을 준다. 본 논문에서는 네트워크 프로세서에 최적화된 기능을 언어 레벨에서 정의한 eFlowC 언어를 사용하고 범용 컴퓨터에서 매스트 및 실행을 할 수 있는 가상머신을 제안한다. 그리고 가상머신 중간언어를 사용하여 가상머신이 설치된 범용 컴퓨터에서 소스코드 재사용 및 확장을 가능하게 한다. 따라서 범용 컴퓨터에서 프로그램 테스트를 통해 신뢰성 높은 프로그램을 작성할 수 있다.

• Korean Journal of Fisheries and Aquatic Sciences
• /
• v.54 no.5
• /
• pp.798-807
• /
• 2021

The directivity characteristics of acoustic transducers for conventional single-beam echo sounders considerably limit the detection of fish-size information in acoustic field surveys. To overcome this limitation, using the split-aperture technique to estimate the direction of arrival of single-echo signals from individual fish distributed within the sound beam represents the most reliable method for fish-size classification. For this purpose, we design and develop a split-beam data acquisition and processing system to obtain fish-size information in conjunction with a 50-kHz single-beam echo sounder. This split-beam data acquisition and processing system consists of a notebook PC, a field-programmable gate array board, an external single-transmitter module with a matching network, and four-channel receiver modules operating at a frequency of 50-kHz. The functionality of the developed split-beam data processor is tested and evaluated. Acoustic measurements in an experimental water tank showed that the developed data acquisition and processing system can be used as a fish-sizing echo sounder to estimate the size distribution of individual fish, although an external single-transmitter module with a matching network is required.

• International Journal of Computer Science & Network Security
• /
• v.21 no.12spc
• /
• pp.570-578
• /
• 2021

Recently, in the field of engineering and scientific and technical calculations, problems of mathematical modeling, real-time problems, there has been a tendency towards rejection of sequential solutions for single-processor computers. Almost all modern application packages created in the above areas are focused on a parallel or distributed computing environment. This is primarily due to the ever-increasing requirements for the reliability of the results obtained and the accuracy of calculations, and hence the multiply increasing volumes of processed data [2,17,41]. In addition, new methods and algorithms for solving problems appear, the implementation of which on single-processor systems would be simply impossible due to increased requirements for the performance of the computing system. The ubiquity of various types of parallel systems also plays a positive role in this process. Simultaneously with the growing demand for parallel programs and the proliferation of multiprocessor, multicore and cluster technologies, the development of parallel programs is becoming more and more urgent, since program users want to make the most of the capabilities of their modern computing equipment[14,39]. The high complexity of the development of parallel programs, which often does not allow the efficient use of the capabilities of high-performance computers, is a generally accepted fact[23,31].

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.1
• /
• pp.67-75
• /
• 1997

This paper presents a virtual-parallel multistage interconnection network (MIN) which provides multipath between processor and memory module. The proposed virtual-parallel MIN network which uses $m{\times}1$ mutiplexer at the input switching block, $1{\times}m$ demultiplexer at the output switching block and logN-1 switching stages has maximum $2{\times}m$ unique paths between processor and memory module. Because it has multi-redundance paths, a number of processors can connect a specific Also, this new virtual-parallel structured MIN network can reduce packet collision possibility at switching block and it has cost. It shown to improve a performance and to be a very simple structure in comparision with MBSF structured MIN.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.9B
• /
• pp.939-946
• /
• 2009

In this paper, we propose a new network ASIP(Application Specific Instruction-set Processor) which was designed for simulation models by a machine descriptions language LISA(Language for Instruction Set Architecture). This network ASIP is aimed for an exclusive engine undertaking packet processing in a router. To achieve the purpose, we added a new necessary instruction set for processing a general ASIP based on MIPS(Microprocessor without Interlock Pipeline Stages) architecture in high speed. The new instructions can be divided into two groups: a classification instruction group and a modification instruction group, and each group is to be processed by its own functional unit in an execution stage. The functional unit was optimized for area and speed through Verilog HDL, and the result after synthesis was compared with the area and operation delay time. Moreownr, it was allocated to the Macro function ana low-level standardized programming language C using CKF(Compiler Known Function). Consequently, we verified performance improvement achieved by analysis and comparison of execution cycles of application programs.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.2
• /
• pp.31-39
• /
• 1998

In this paper, we have presented a quantitative performance effect of CCP(Call Control Processor) when SAAL(Signalling ATM Adaptation Layer) function is distributed from CCP to SIMs(Subscriber Interface Modules) in an ATM switching system with distributed architecutre. For the performance analysis, SLAM II simulation language is used and subscriber signalling messageand inter-processor communication messages according to Q.2931 based local call processing procedure are taken into consideration in the proposed queuing network model. The results of simulation are compared with in case of processing SAAL function on CCP. It is observed that the processing utilization of CCP reach 24,000 BHCA and 25,700 BHCAwhen SAAL function load amounts to 10% and 20% of the processing time of the total message, respectively. These values shows that the processing utilization of CCP is alleviated about 7% in comparison with 2,000 BHCA in case that SAAL function is carried out on CCP. Consquently, it is shown that we have to consider seriously how to distribute the functions concerning call processing in a large cale ATM switching system architecture accomodating a number of SIMs.

• The Journal of the Korea Contents Association
• /
• v.5 no.3
• /
• pp.183-191
• /
• 2005

In a sender-initiated load sharing algorithms, sender(overloaded processor) continues to send unnecessary request messages for load transfer until receiver(underloaded processor) is found while the system load is heavy. Therefore, it yields many problems such as low CPU utilization and system throughput because of inefficient inter-processor communications until the sender receives an accept message from the receiver in this environment. This paper presents an approach based on genetic algorithm(GA) for dynamic load sharing in heterogeneous distributed systems. In this scheme the processors to which the requests are sent off is determined by the proposed GA to decrease unnecessary request messages.

• Proceedings of the KIEE Conference
• /
• 1999.07f
• /
• pp.2578-2580
• /
• 1999

In this paper, an embedded micro processor based resistance spot welding controller is introduced which has been recently developed by Hyosung Co. Ltd. The performance of rapid and constant high current control is tested experimentally. This paper shows configurations of measuring system for high current and realtime RMS conversion techniques of sampled discrete data. A digital proportional control is adopted for this system and the result shows that this new product is working well at wide range of welding current and the performance is improved compared with some other commercially available controllers that are widely used in our industries. User friendly MMI system and a computer network system to monitor each welding processes are also presented.

• Journal of the Korean Professional Engineers Association
• /
• v.16 no.1
• /
• pp.4-12
• /
• 1983

Data communication has historically evolved from leased lines, to use of the public telephone network, and eventually to dedicated(exclusive) data networks. It requires an enormous amount of money for establishing a separate and independent data network at the beginning stage. No country has ever adopted this method In the Republic of Korea too the age of leased circuits is passing and it is scheduled to open the public telephone network to the data transmission and to install packet mode processor in the last half of 1983. This paper presents a survey on characteristics of the public telephone network in Seoul and a future development of the data communication of Korea.