• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.3
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• pp.307-322
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• 1992

For designing the radar integrated data network, we construct the network structure with a spatial hieratchy decomposition scheme. The RIDN can be decomposed into several subent classes, those of which are composed of the several group classes of radar sites, In a group class. The communication nodes of a radar site are modeled by the software modules formulated with the statistical attributes of discrete events. And we get the analysis over the network through the separately constructed infra group level models which were coded with the C language.From the result of the simulation. We could findthe fact that the data integration system;s performance approaches to the theordtically calculated value after being stable. And also we could get the packet processing status of a communication module’s inner processor which is difficult to oberve through the mathematical calculation tin the subnet model of the integrated data network.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2001.12a
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• pp.255-258
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• 2001

This paper is implementation of cellular automata neural network system which is a living creatures' brain using evolving hardware concept. Cellular automata neural network system is based on the development and the evolution, in other words, it is modeled on the ontogeny and phylogeny of natural living things. The proposed system developes each cell's state in neural network by CA. And it regards code of CA rule as individual of genetic algorithm, and evolved by genetic algorithm. In this paper we implement this system using evolving hardware concept Evolving hardware is reconfigurable hardware whose configuration is under the control of an evolutionary algorithm. We design genetic algorithm process for evolutionary algorithm and cells in cellular automata neural network for the construction of reconfigurable system. The effectiveness of the proposed system is verified by applying it to time-series prediction.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.620-623
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• 2000

A very simple control approach using neural network for the robust position control of a Permanent Magnet Synchronous Motor(PMSM) is presented The linear quadratic controller plus feedforward neural network is employed to obtain the robust PMSM system approximately linearized using field-orientation method for an AC servo. The neural network is trained in on-line phases and this neural network is composed by a fedforward recall and error back-propagation training. Since the total number of nodes are only eight this system can be easily realized by the general microprocessor. During the normal operation the input-output response is sampled and the weighting value is trained multi-times by error back-propagation method at each sample period to accommodate the possible variations in the parameters or load torque. And the state space analysis is performed to obtain the state feedback gains systematically. IN addition the robustness is also obtained without affecting overall system response. This method is realized by a floating-point Digital Singal Processor DS1102 Board (TMS320C31) The basic DSP software is used to write C program which is compiled by using ANSI-C style function prototypes.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.4
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• pp.371-376
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• 2004

Distributed Network Protocol Version 3.0 (DNP3.0) is the communication protocol developed for the interoperability between a RTU and a central control station of SCADA in the power utility industry. In this paper DNP3.0 is implemented by using HDL with FPGA and C program on Hitachi H8/532 processor. DNP3.0 is implemented from physical layer to network layer in hardware level to reduce the computing load on a CPU. Finally, the ASIC for DNP3.0 has been manufactured from Hynix Semiconductor. The commercial feasibility of the hardware through the communication test with ASE2000 and DNP Master Simulator is performed. The developed protocol becomes one of IP, and can be used to implement SoC for the terminal device in SCADA systems. Also, the result can be applicable to various industrial controllers because it is implemented in HDL.

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.77-81
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• 2006

Because of the rapid increasing of network user, there are some problems to tolerate the network overhead. Recently, the research and technology of the user-level for high performance and low latency than TCP/IP which relied upon the kernel for processing the messages. For example, there is an Infiniband technology. The Infiniband Trade Association (IBTA) has been proposed as an industry standard for both communication between processing node and I/O devices and for inter-processor communication. It replaces the traditional bus-based interconnect with a switch-based network for connecting processing node and I/O devices. Also Infiniband uses RDMA (Remote DMA) for low latency of CPU and OS to communicate between Remote nodes. In this paper, we develop the SRP (SCSI RDMA Protocol) which is Storage Access Protocol on Infiniband network. And will compare to FC (Fibre Channle) based I-SCSI (Internet SCSI) that it is used to access storage on Etherent Fabric.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.7
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• pp.594-601
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• 2000

EIA-709.1 Control Network Protocol is the basic protocol of LonWorks systems that is emerg-ing as a fieldbus device. In this paper the protocol is implemented by using VHDL with FPGA and C program on an Intel 8051 processor. The protocol from the physical layer to the network layer of EIA-709.1 is im-plemented in a hardware level,. So it decreases the load of the CPU for implementing the protocol. We verify the commercial feasibility of the hardware through the communication test with Neuron Chip. based on EIA-709.1 protocol which is used in industrial fields. The developed protocol based on FPGA becomes one of IP can be applicable to various industrial field because it is implemented by VHDL.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.625-627
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• 2005

본 논문은 인텔사의 IXP2400 네트워크 프로세서를 이용하여 IPv6 multicast-enabled 라우터 개발의 예비단계로서 IPv6 멀티캐스트 모듈의 전체적인 설계 및 구현을 다룬다. 특히, 마이크로 엔진할당, IPv6 멀티캐스트 마이크로 블록 및 패킷 복사 마이크로 블록에 중점을 둔다. 우리의 IPv6 멀티캐스트 포워딩 모듈의 성능측정 결과는 이론적 한계치의 $86\%$였다.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.6
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• pp.247-251
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• 2021

We propose a protocol for Ethernet-based industrial real-time communication networks. In the protocol, the master periodically transmits control frames to all slaves, and the ring-type network topology is selected to achieve high-speed transmission speed. The proposed protocol is implemented in the form of both firmware and Linux kernel modules. To improve the transmission speed, the MAC address table is disabled in the firmware implementation, and the NAPI function of the Ethernet driver is removed in the Linux kernel module implementation. A network experiment environment is built with four ARM processor-based embedded systems and network operation experiments are performed for various frame sizes. From the experimental results, it is verified that the proposed protocol normally operates, and the firmware implementation shows better transmission speed than the Linux kernel module implementation.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.691-698
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• 2006

TCP/IP Offload Engine (TOE) is a technology that processes TCP/IP on a network adapter instead of a host CPU to reduce protocol processing overhead from the host CPU. There have been some approaches to implementing TOE: software TOE based on an embedded processor; hardware TOE based on ASIC implementation; and hybrid TOE in which software and hardware functions are combined. In this paper, we designed software modules and hardware modules for a hybrid TOE on an FPGA that had two processor cores. Software modules are based on the embedded Linux. Hardware modules are for data transmission (TX) and reception (RX). One core controls the TX path and the other controls the RX path of the Linux. This TX/RX path separation mechanism can reduce task switching overheads between processes and overcome poor performance of single embedded processor. Hardware modules deal with creating headers for outgoing packets, processing headers of incoming packets, and fetching or storing data from or to the host memory by DMA. These can make it possible to improve the performance of data transmission and reception. We proved performance of the TOE with separated transmission and reception paths by performing experiments with a TOE network adapter that was equipped with the FPGA having processor cores.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.6
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• pp.9-16
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• 2011

Due to the development and proliferation of ubiquitous technologies and services, various sensor network applications are being appeared on the stage. The needs for algorithms requiring sensor data fusion and complex signal processing with a high-performance processor such as a digital signal processor are also increased. However, it is difficult to use such processor for the low-power sensor network operating with a battery because of power consumption. This paper proposes a hybrid-type sensor module architecture supporting wakeup/sleep software framework for the wireless sensor node and shows the implemented sensor node platform and performances focused on the energy consumption and wakeup time.