• Journal of KIISE:Information Networking
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• v.32 no.2
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• pp.254-260
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• 2005

In the guaranteed service, a real-time scheduling algorithm must achieve both high level of network utilization and scalable implementation. Here, network utilization indicates the number of admitted real-time sessions. Unfortunately, existing scheduling algorithms either are lack of scalable implementation or can achieve low network utilization. For example, scheduling algorithms based on time-stamps have the problem of O(log N) scheduling complexity where N is the number of sessions. On the contrary, round-robin algorithms require O(1) complexity. but can achieve just a low level of network utilization. In this paper, we propose a scheduling algorithm that can achieve high network utilization without losing scalability. The proposed algorithm is a Hierarchical Round-Robin (H-RR) algorithm that utilizes multiple rounds with different interval sizes. It provides latency bounds similar to those by Packet-by-Packet Generalized Processor Sharing (PGPS) algorithm using a sorted-Priority queue. However, H-RR requires a constant time for implementation.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.1
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• pp.15-21
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• 2010

This paper proposes the multimedia fingerprinting code insertion algorithm when video content is distributed in P2P environment, and designs the collusion codebook SRP(Small RISC Processor) embedded system for the collusion attack prevention. In the implemented system, it is detecting the fingerprinting code inserted in the video content of the client user in which it requests an upload to the web server and in which if it is certified content then transmitted to the streaming server then the implemented system allowed to distribute in P2P network. On the contrary, if it detects the collusion code, than the implemented system blocks to transmit the video content to the streaming server and discontinues to distribute in P2P network. And also it traces the colluders who generate the collusion code and participates in the collusion attack. The collusion code of the averaging attack is generated with 10% of BIBD code v. Based on the generated collusion code, the codebook is designed. As a result, when the insert quantity of the fingerprinting code is 0.15% upper in bitplane 0~3 of the Y(luminance) element of I-frame at the video compression of ASF for a streaming service and MP4 for an offline offer of video content, the correlation coefficient of the inserted original code and the detected code is above 0.15. At the correlation coefficient is above 0.1 then the detection ratio of the collusion code is 38%, and is above 0.2 then the trace ratio of the colluder is 20%.

• Journal of the Institute of Convergence Signal Processing
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• v.1 no.1
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• pp.1-6
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• 2000

In this paper, the hybrid system of HMM and neural network is proposed and show better recognition rate of the post-process procedure which minimizes the process error of recognition than that of HMM(Hidden Markov Model) only used. After the HMM training by training data, testing data that are not taken part in the training are sent to HMM. The output probability from HMM output by testing data is used for the training data of the neural network, post processor. After neural network training, the hybrid system is completed. This hybrid system makes the recognition rate improvement of about $4.5\%$ in MLP and about $2\%$ in RBFN and gives the solution to training time of conventional hybrid system and to decrease of the recognition rate due to the lack of training data in real-time speech recognition system.

• Journal of Electrical Engineering and information Science
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• v.1 no.1
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• pp.1-9
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• 1996

A key issue in spoken language processing has become the integration of speech understanding and natural language processing(NLP). This paper presents a parallel computational model for the integration of speech and NLP. The model adopts a hierarchically-structured knowledge base and memory-based parsing techniques. Processing is carried out by passing multiple markers in parallel through the knowledge base. Speech-specific problems such as insertion, deletion, and substitution have been analyzed and their parallel solutions are provided. The complete system has been implemented on the Semantic Network Array Processor(SNAP) and is operational. Results show an 80% sentence recognition rate for the Air Traffic Control domain. Moreover, a 15-fold speed-up can be obtained over an identical sequential implementation with an increasing speed advantage as the size of the knowledge base grows.

• Journal of Digital Convergence
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• v.12 no.1
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• pp.333-338
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• 2014

Zigbee is a wireless communication technology optimized for WSN (Wireless Sensor Network) environment. A WSN gateway is used for node control and data transmission. However, a fixed-type gateway can restrict the flexibility of the WSN environment. A smartphone-mounted high-performance processor and Android OS can be easily used in a mobile WSN gateway. In this paper, we proposed a mobile WSN gateway based on Android smartphones. In the proposed system, a Zigbee sensor module is connected with a smartphone via USB (Universal Serial Bus) port. We also implemented an Android application for the mobile WSN gateway.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.94.4-94
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• 2002

Traditional control systems that consist of sensors, actuators and a controller centralized and connected with point-to-point links, have become distributed because of their performance limits and maintenance problems. Sensors and actuators are changed to smart devices having a processor and these devices and controllers are connected with fieldbuses such as Profibus, FIP, CAN, LonWorks and so on. Because they are distributed, it takes any delay to transmit data from sensor to controller and data from controller to actuator according to network characteristic. Also, the execution times of tasks in a node are not regular and depend on the node characteristic and the number of tasks and so on...

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.837-840
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• 1999

In this paper, we design and verify the hardware circuit that performs PLCP(Physical Layer Convergence Protocol) protocol functions of physical layer in IEEE 802.11 frequency hopping WLAN(Wireless Local Area Network). Altera MAX＋PLUS I $I^{〔1〕}$ is used as a design tool. The designed circuit consists of control register module to interface with upper layer, FIFO module to transmit/receive data with upper layer, TX function module, and RX function module. It is verified that the developed circuit conforms well to the IEEE 802.11 standard specification and can support both 1Mbps and 2 Mbps transmission rate by simulation. The developed circuits can be utilized for the implementation of protocol processor in wireless LAN areas.

• Journal of Convergence for Information Technology
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• v.9 no.1
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• pp.92-98
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• 2019

Due to the development of hologram display technology, various studies are being conducted to provide realistic contents for augmented reality. In the case of the HMD for hologram, since augmented reality objects must be rendered by a small processor, it is necessary to use a low-capacity content. To solve this problem, there is a need for a technique of rendering resources by providing resources through a network. In the case of the existing augmented reality system, there is no problem of contents modulation because the resources are loaded and rendered in the internal storage space. However, when providing resources through the network, security problems such as content tampering and malicious code insertion should be considered. Therefore, in this paper, we propose a network rendering technique applying security techniques to provide augmented reality contents in a holographic HMD device.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12B
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• pp.1236-1243
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• 2010

The perimeter defense system was created and its characteristics were evaluated. It was designed to utilize the fiber sensing device, namely OTDR(Optical Time Domain Reflectometer) which has been used for the maintenance of the optical communication network. An OTDR was constituted by a pulse laser with the nature of 1310nm, +15dBm for the observation of 400 meter optical fence. The high-speed 32-bit processor(S3C2440) has applied to MPU(Main Processor Unit) which helps to improve the performance of OTDR algorithms. Consequently, the maximum error was 0.84 meter on the performance test of the 10km monitoring and the pass criteria of ${\pm}1m$ satisfied in all the sections. The alarm delay time was under 3 sec after detecting the disorder. For the case of secondary trespassing after primary trespassing, the optical switch was installed in OTDR to monitor the secondary trespassing and to measure the multi-point detection. Therefore, this paper shows that the detections of secondary trespassing and multi-point is possible by means of optical switch.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.88-95
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• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.