• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2755-2757
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• 2002

In this paper, we propose a now architecture for hardware implementation of digital neural network. By adopting flexible ladder-style bus and internal connection network into traditional SIMD-type digital neural network architecture, the proposed architecture enables fast processing that is based on parallelism, while does not abandon the flexibility and extensibility of the traditional approach. In the proposed architecture, users can change the network topology by setting configuration registers. Such reconfigurability on hardware allows enough usability like software simulation. We implement the proposed design on real FPGA, and configure the chip to multi-layer perceptron with back propagation for alphabet recognition problem. Performance comparison with its software counterpart shows its value in the aspect of performance and flexibility.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.5
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• pp.41-51
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• 1996

In this paper, anew parallel processing system based on a cluster architecture which provides scalability of a parallel processing system while maintains shared memory multiprocessor characteristics is proposed. In recent days low cost, high performnce microprocessors have led to construction of large scale parallel processing systems. Such parallel processing systems provides large scalability but are mainly used for scientific applications which have large data parallelism. A shared memory multiprocessor system like TICOM is currently used as aserver for the commercial application, however, the shared memory multiprocessor system is known to have very limited scalability. The proposed architecture can support scalability and performance of the parallel processing system while it provides adaptability for the commerical application, hence it can overcome the limitation of the shared memory multiprocessor. The architecture and characteristics of the proposed system shall be described. A proprietary hierarchical crsossbar network is designed for this system, of which the protocol, routing and switching technique and the signal transfer technique are optimized for the proposed architecture. The design trade-offs for the network are described in this paper and with simulation usihng the SES/workbench, it is explored that the network fits to the proposed architecture.

• ETRI Journal
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• v.31 no.2
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• pp.111-120
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• 2009

Network-on-chip (NoC) architecture provides a highper-formance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in $6{\times}6$6, $8{\times}8$, and $10{\times}10$ mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit-switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10A
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• pp.1717-1726
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• 2001

본 논문에서는 CORBA(Common Object Request Architecture)기반의 TINA(Telecommunications Information Networking Architecture) 분산체계에서 통신망 하부 장비들이 SNMP(Simple Network Management Protocol) 혹은 TMN(Telecommunications Management Network) 체계로 혼재되어 관리되는 네트워크의 NE(Network Element)들을 효율적으로 통합 관리할 수 있는 Generic Interface Adaptor(GIA)를 제안하고 이를 설계 및 구현하였다. GIA는 message mapping, protocol conversion 및 DBMS를 이용한 Object Abstract Translation(OAT)을 통해서 각 관리체계에 맞도록 관리정보를 변환시키며, 이를 통해 TINA EML(Element Management Layer) component와 SNMP NE agent 간의 상호연동을 가능하게 한다.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.820-824
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• 2004

Personal Robot System in developing, have a module architecture, each module are connected through heterogeneors network systems like Ethernet, WLAN (802.11), IEEE1394 (Firewire), Bluetooth, USB, CAN, or RS-232C. In developing personal robot system we think that the key of robot performance is interoperability among modules. Each network protocol are well connected in the view of network system for the interoperability. So we make a bridging architecture that can routing, converting, transporting data packets with matcing each network's properties. Furthermore we suggest a advanced design scheme for realtime / non-realtime and control signal (short, requiring hard-realtime) / multimedia data (large, requiring soft-realtime). By some application systems, we could test performance, interoperability and stability. In this paper, we show our design concept, middleware architecture, and some applications systems using this middleware.

• Smart Media Journal
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• v.1 no.1
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• pp.27-35
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• 2012

In this paper, the performance analysis for multimedia video codec(MPEG-4, H.264) on on-chip network communication architecture is presented. The On-Chip Network (OCN) is the new communication architecture of multimedia SoC design that overcomes the limits of On-Chip Bus architecture by providing higher data traffic bandwidth, reusability and higher scalability. We compared the performance of MPEG-4, H.264 decoder based on-chip network and AMBA on-chip bus. Experimental results show that the performance of MPEG-4, H.264 based on on-chip network is improved over 33~56% compared to the design based on AMBA on-chip bus.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.537-540
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• 2000

In this paper, we propose and design new architecture of the modified Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. The switch scheme is that two packets may arrive on different inputs destined for the same output. We have analyzed the maximum throughput of the revised switch. The result of the analyses shows good agreement simulation and if we adopt such architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about lloio when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL.

• Proceedings of the IEEK Conference
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• summer
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• pp.87-91
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• 2004

This research presents distributed database and knowledge-base modeling approach for intelligent product design system. The product design information in this study is described by a collection of rules and design knowledge that are utilized according to the product development procedures. In this work, a network-based architecture has been developed to enable dispersed designers to simultaneously accomplish remote design tasks. A client/server communication diagram has also been proposed to facilitate consistent primary information modeling for multi-user access and reuse of designed results. An intelligent product design system has been studied with the concepts of distributed database and network-based architecture in order to support concurrent engineering design and automatic design part assembly. The system provides the capability of composing new designs from proper design elements stored in the database and knowledge-base. The distributed intelligent product design is applied to the design of an automobile part as an example.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.11
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• pp.1167-1178
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• 1991

In this paper, we review the characteristics of battle field, consider required properties of mobile radio network, and design network control architecture proper to battle field network. Also we design distributed algorithm which constructs network control architecture and transmission schedule. For the information of network connectivity and the immediate reconfiguration caused by failure, loss, or movement of nodes, configuration and transmission schedule, algorithms are to be executed periodically and for entire network reliability, algorithms must to be executed fully distributedly. At the time of loss or failure of primary local control node, we suggest the method which diminishes transmission delay. We explain the operation of network with examples. Finally designed algorithms are verified and analized by computer simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.8B
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• pp.525-534
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• 2005

This paper proposes the architecture and the methods of security network management for auto-configuration of security systems by extending the existing policy-based network management architecture. The architecture and the methods proposed in this paper enable a security management sewer to automatically decide the best-suited security policy to apply to a security system and the most effective and efficient security system to perform security policy rule, based on the role and capability information of security systems and the role and time information of security policy. For integrated control of network system and security system, this paper also proposes SNMP protocol based security network topology map generator. To show the excellence of the proposed architecture and methods, we simulate and evaluate the automatic response against attacks.