• Transactions on Electrical and Electronic Materials
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• 제14권2호
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• pp.78-81
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• 2013

$0.95(Na_{0.5}K_{0.5})NbO_3-0.05BaTiO_3+0.2wt%\;Ag_2O$ (hereafter, No excess NKN) ceramics and $0.95(Na_{0.5}K_{0.5})NbO_3-0.05BaTiO_3+0.2wt%\;Ag_2O$ with excess $(Na_{0.5}K_{0.5})NbO_3$ (hereafter, Excess NKN) were fabricated by the conventional solid state sintering method, and their phase transition properties and dielectric properties were investigated. The crystalline structure of No excess NKN ceramics and Excess NKN ceramics were shown characteristics of polymorphic phase transition (hereafter, PPT), especially shift from the orthorhombic to tetragonal phase by increasing sintering temperature range from $1,100^{\circ}C$ to $1,200^{\circ}C$. Also, the temperature coefficient of capacitance (hereafter, TCC) of No excess NKN ceramics and Excess NKN ceramics from $-40^{\circ}C$ to $100^{\circ}C$ was measured to evaluate temperature stability for applications in cold regions. The TCC of No excess NKN and Excess NKN ceramics showed positive TCC characteristics at a temperature range from $-40^{\circ}C$ to $100^{\circ}C$. Especially, Excess NKN showed a smaller TCC gradient than those of Excess NKN ceramics in range from $-40^{\circ}C$ to $100^{\circ}C$. Therefore, NKN piezoelectric ceramics combined with temperature compensated capacitor having negative temperature characteristics is desired for usage in cold regions.

• 한국결정성장학회지
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• 제24권3호
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• pp.106-110
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• 2014

Atomic layer deposition(ALD)을 이용하여 $Al_2O_3$ 박막을 형성하고 이에 대한 패시베이션 특성에 대한 연구를 수행하였다. ALD로 증착된 $Al_2O_3$ 박막은 $400^{\circ}C$ 5분간 후속 열처리 공정 후에도 $Al_2O_3$ - 실리콘 계면 반응 없이 비정질 상태를 유지할 만큼 구조적으로 안정한 특성을 나타내었다. 후속 열처리 후 $Al_2O_3$ 박막의 패시베이션 특성이 향상되었으며, 이는 field effective 패시베이션과 화학적 패시베이션 효과가 동시에 상승에 기인하는 것으로 판단된다. $Al_2O_3$ 박막의 음고정 전하를 정량적으로 평가하기 위해서 후속 열처리 공정을 거친 $Al_2O_3$ 박막을 이용하여 metal-oxide-semiconductor(MOS) 소자를 제작하고 capacitance-voltage(C-V) 분석을 수행하였다. C-V 결과로부터 추출된 flatband voltage($V_{FB}$)와 equivalent oxide thickness(EOT)의 관계식을 통하여 $Al_2O_3$ 박막의 고정음전하는 $2.5{\times}10^{12}cm^{-2}$로 계산되었으며, 이는 본 연구에서 제시된 $Al_2O_3$ 박막 공정이 N-type 실리콘 태양전지의 패시베이션 공정에 응용 가능하다는 것을 의미한다.

• 한국정보전자통신기술학회논문지
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• 제14권6호
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• pp.479-486
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• 2021

본 논문에서는 신호감지회로(Signal Sensing Circuit : SSC)를 추가하여 2개의 루프로 구성된 단일 커패시터 루프필터를 가진 극소형 위상고정루프(Phase Locked Loop : PLL)를 제안하였다. 위상고정루프 크기를 극단적으로 줄이기 위하여 가장 많은 면적을 차지하는 수동소자 루프필터를 극소형 단일 커패시터(2pF)로 설계하였다. 신호감지회로가 포함된 내부 부궤환 루프 출력이 외부 부궤환 루프의 단일 커패시터 루프필터 출력에 부궤환 역할을 하여 제안한 극소형 위상고정루프가 안정적으로 동작하도록 설계하였다. 위상고정루프 출력 신호 변화를 감지하는 신호 감지 회로는 루프필터의 커패시턴스 전하량을 조절하여 위상고정루프 출력 주파수의 초과 위상변이를 줄였다. 제안된 구조는 기존 구조에 비해 1/78 정도의 작은 커패시터를 가짐에도 불구하고 지터 크기는 10% 정도 차이가 난다. 본 논문의 위상고정루프는 1.8V 180nm 공정을 사용하였고, Spice를 통해 안정하게 동작하는 시뮬레이션 결과를 보여주었다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1364-1369
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• 2005

In this paper, we have identified the mechanism of C-V hysteresis behavior often observed in pentacene organic thin-film transistors (OTFTs). The capacitance-voltage (C-V) characteristics were measured for pentacene OTFTs fabricated on glass substrates with MoW as gate/source/drain electrode and TEOS $SiO_2$ as gate insulator. The measurements were made at room temperature and elevated temperatures. From the room temperature measurements, we found that the hysteresis behavior was caused by hole injection into the gate insulator from the pentacene semiconductor for large negative gate voltages, resulting in the negative flat-band voltage shift. However electron injection was observed only at elevated temperatures

• Advances in materials Research
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• 제2권1호
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• pp.1-13
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• 2013

Lead-free compound $(Na_{0.5}Bi_{0.5})(Zr_{0.75}Ti_{0.25})O_3$ was prepared using conventional ceramic technique at $1070^{\circ}C$/4h in air atmosphere. X-ray diffraction analysis showed the formation of single-phase orthorhombic structure. Permittivity data showed low temperature coefficient of capacitance ($T_{CC}{\approx}5%$) up to $100^{\circ}C$. Complex impedance studies indicated the presence of grain boundary effect, non-Debye type dielectric relaxation and evidences of a negative temperature coefficient of resistance. The ac conductivity data were used to evaluate the density of states at Fermi level and apparent activation energy of the compound.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1996년도 춘계학술대회 논문집
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• pp.635-640
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• 1996

A thermo-elastic system in the production machine has highly nonlinear dynamic characteristics. In general, the finite element method is utilized for accurate analysis. However, it requires large computing time. Thus, thermo-elastic systems are usuallymodeled as electric and fluid system using lumped para,eter. In this paper. we propose the bondgraph model and transient simulation methodology of thermo-elastic system in consideration of various boundary and joint contact conditions. Consequently, the proposed method ensures a possibility of its on-line compensation about undesirable phenomena by using real time estimate process and electronic cooling device for thermal appropriate behavior. Thermo-elastic model consisting of bush and shaft including contact condition is presented.

• 한국응용과학기술학회지
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• 제28권3호
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• pp.329-334
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• 2011

The electrochemical performances of an asymmetric hybrid capacitor were investigated using $LiFePO_4$ as the positive electrode and active carbon fibers(ACF) as the negative electrode. The electrochemical behaviors of a nonaqueous hybrid capacitor were characterized by constant current charge/discharge test. The specific capacitance using $LiFePO_4$/ACF electrode turned out to be $0.87F/cm^2$ and the unit cell showed excellent cycling performance. This hybrid capacitor was able to deliver a specific energy as high as 178 Wh/kg at a specific power of 1,068 W/kg.

• Journal of information and communication convergence engineering
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• 제13권4호
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• pp.257-263
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• 2015

In this study, organic field-effect transistors (OFETs) using a copper phthalocyanine (CuPc) material as an active layer and SiO₂ as a gate insulator were fabricated with varying active layer thicknesses and channel lengths. Further, using a thermal evaporation method in a high-vacuum system, we fabricated a CuPc FET device of the top-contact type and used Au materials for the source and drain electrodes. In order to discuss the channel formation and FET characteristics, we observed the typical current-voltage characteristics and calculated the threshold voltage of the CuPc FET device. We also found that the capacitance reached approximately 97 pF at a negative applied voltage and increased upon the accumulation of carriers at the interface of the metal and the CuPc material. We observed the typical behavior of a FET when used as an n-channel FET. Moreover, we calculated the threshold voltage to be about 15-20 V at V_DS = -80 V.

• ETRI Journal
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• 제31권6호
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• pp.755-764
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• 2009

This paper presents a switched self-biasing and a tail current-shaping technique to suppress the 1/f noise from a tail current source in differential cross-coupled inductance-capacitance (LC) voltage-controlled oscillators (VCOs). The proposed LC VCO has an amplitude control characteristic due to the creation of negative feedback for the oscillation waveform amplitude. It is fabricated using a 0.13 ${\mu}m$ CMOS process. The measured phase noise is -117 dBc/Hz at a 1 MHz offset from a 4.85 GHz carrier frequency, while it draws 6.5 mA from a 0.6 V supply voltage. For frequency tuning, process variation, and temperature change, the amplitude change rate of the oscillation waveform in the proposed VCO is 2.1 to 3.2 times smaller than that of an existing VCO with a fixed bias. The measured amplitude change rate of the oscillation waveform for frequency tuning from 4.55 GHz to 5.04 GHz is 131 pV/Hz.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 춘계학술대회
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• pp.154-156
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• 2016

본 논문에서는 기존 위상고정루프의 아날로그 루프 필터 형태와 달리 전압제어발진기의 출력 신호로 동작하는 이산 루프 필터를 사용하여 크기는 작으면서 안정하게 동작하는 위상고정루프를 제안하였다. 샘플링과 부궤환 역할을 하는 스위치와 결합된 작은 크기의 커패시터로 하나의 칩으로 집적화가 가능한 위상고정루프는 1.8V 0.18um CMOS 공정을 이용하여 설계 하였다.