• Proceedings of the Korean Magnestics Society Conference
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• 2004.12a
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• pp.59-60
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• 2004

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2892-2898
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• 2015

We propose a new Double-Independent-Gate Ambipolar Silicon-Nanowire Field Effect Transistor(DIG Ambi-SiNWFET). The proposed transistor has two types of gate such as polarity gate and control gate. The polarity gate determines the operation that the gate bias controls NMOSFET or PMOSFET. The voltage of control gate controls the current characteristic of the transistor. We investigated systematically work functions of the two gates and source/drain to operate ambipolar current-voltage characteristics using 2D device simulator. When the work functions of polarity gate, control gate and source/drain are 4.75eV, 4.5eV, and 4.8eV, respectively, it showed the obvious ambipolar characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.429.2-429.2
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• 2014

ZnO nanowire is known as synthesizable and good mechanical properties. And, stimuli-responsive polymer is widely used in the application of tunable sensing device. So, we combined these characteristics to make precise tunable sensing devise. In this work, we investigate the dependence of ZnO nanowire alignment and morphology on si substrate using nanosphere template with various conditions via hydrothermal process. Also, pH-temperature dependant tuning ability of nanostructure was studied. The brief experimental scheme is as follow. First, Zno seed layer was coated on a si wafer ($20{\times}20mm$) by spin coater. And then $1.15{\mu}m$ sized close-packed PS nanospheres were formed on a cleaned si substrate by using gas-liquid-solid interfacial self-assembly method. After that, zinc oxide nanowires were synthesized using hydrothermal method. Before the wire growth, to specify the growth site, heat treatment was performed. Finally, NIPAM(N-Isopropylacrylamide) was coated onto as-fabricated nanostructure and irradiated by UV light to form the PNIPAM network. The morphology, structures and optical properties are investigated by FE-SEM(Field Emission Scanning electron Microscopy), XRD(X-ray diffraction), OM(Optical microscopy), and WCA(water contact angle).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.879-882
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• 2015

In this work, we have analyzed the characteristics of vertical nanowire GAA MOSFET according to channel width and the type of channel doping through the simulation. First, we compared and analyzed the characteristics of designed structures which have tilted shapes that ends of drains are fixed as 20nm and ends of sources are 30nm, 50nm, 80nm and 110nm. Second, we designed the rectangular structure which has uniform width of drain, channel and source as 50nm. We used it as a standard and designed trapezoidal structure which is tilted so that the end of drain became 20nm and reverse trapezoidal structure which is tilted so that the end of source became 20nm. We compared and analyzed the characteristic of above three structures. For the last, we used the rectangular structure, divided its channel as five parts and changed the type of the five parts of doping concentration variously. In the first simulation, when the channel width is the shortest, in the second, when the structure is trapezoid, in the third, when the center of channel is high doped show the best characteristics.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.24.2-24.2
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• 2009

Nanostuctures such as nanodot and nanowire have been extensively studied as building blocks for nanoscale devices. However, the direct growth of the nanostuctures at the desired position is one of the most important requirements for realization of the practical devices with high integrity. Self-assembled nanotemplate is one of viable methods to produce highly-ordered nanostructures because it exhibits the highly ordered nanometer-sized pattern without resorting to lithography techniques. And selective epitaxial growth (SEG) can be a proper method for nanostructure fabrication because selective growth on the patterned openings obtained from nanotemplate can be a proper direction to achieve high level of control and reproducibility of nanostructucture fabrication. Especially, SiGe has led to the development of semiconductor devices in which the band structure is varied by the composition and strain distribution, and nanostructures of SiGe has represented new class of devices such nanowire metal-oxide-semiconductor field-effect transistors and photovoltaics. So, in this study, various shaped SiGe nanostructures were selectively grown on Si substrate through ultrahigh vacuum chemical vapor deposition (UHV-CVD) of SiGe on the hexagonally arranged Si openings obtained using nanotemplates. We adopted two types of nanotemplates in this study; anodic aluminum oxide (AAO) and diblock copolymer of PS-b-PMMA. Well ordered and various shaped nanostructure of SiGe, nanodots and nanowire, were fabricated on Si openings by combining SEG of SiGe to self-assembled nanotemplates. Nanostructure fabrication method adopted in this study will open up the easy way to produce the integrated nanoelectronic device arrays using the well ordered nano-building blocks obtained from the combination of SEG and self-assembled nanotemplates.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.245-245
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• 2009

l-D nanostructured materials have much more attention because of their outstanding properties and wide applicability in device fabrication. Copper oxide(CuO) has been realized as a p-type metal oxide semiconductor with narrow band gap of 1.2 -1.5eV. Copper oxide nanostructures can be synthesized by various growth method such as oxidation reaction, thermal evaporation thermal decomposition, sol-gel. and Mostly CuO nanowire prepared on the Cu substrate such as Copper foil, grid, plate. In this study, CuO NWs were grown by thermal oxidation (at various temperatures in air (1 atm)) of Cu metal deposited on CuO (20nm)/$SiO_2$(250nm)/Si. A 20nm-thick CuO layer was used as an adhesion layer between Cu metal and $SiO_2$

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.182-189
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• 2011

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting $Ge-Al_xGa_{1-x}As-Ge$ system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2).

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.5.2-5.2
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• 2009

From 10 years ago, the development of nano-devices endeavored to achieve reconstruction of information technology (IT) and nano technology (NT) industry. Among the many materials for the IT and NT industry, zinc oxide (ZnO) is a very promising candidate material for the research of nano-device development. Nano-structures of ZnO-based materials were grown easily via various methods and it attracts huge attention because of their superior electrical and optical properties for optoelectronic devices. Recently, among the various growth methods, MOCVD has attracted considerable attention because it is suitable process with benefits such as large area growth, vertical alignment, and accurate doping for nano-device fabrication. However, ZnO based nanowires grown by MOCVD process were had the principal problems of 1st interfacial layers between substrate and nanowire, 2nd a broad diameter (about 100 nm), and 3rd high density, and 4th critical evaporation temperature of Zinc precursors. In particular, the growth of high performance nanowire for high efficiency nano-devices must be formed at high temperature growth, but zinc precursors were evaporated at high temperature.These problems should be repaired for materialization of ultra high performance quantum devices with quantum effect. For this reason, we firstly proposed the growth method of vertical aligned slim MgZnO nanowires (< 10 nm) without interfacial layers using self-phase separation by introduced Mg at critical evaporation temperature of Zinc precursors ($500^{\circ}C$). Here, the self-phase separation was reported that MgO-rich and the ZnO-rich phases were spontaneously formed by additionally introduced Mg precursors. In the growth of nanowires, the nanowires were only grown on the wurzite single crystal seeds as ZnO-rich phases with relatively low Mg composition (~36 at %). In this study, we investigated the microstructural behaviors of self-phase separation with increasing the Mg fluxes in the growth of MZO NWs, in order to secure drastic control engineering of density,diameter, and shape of nanowires.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.546-550
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• 2013

We propose a novel negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) by combining pn junction diode with depletion mode nanowire (NW) transistor, which suppress the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) Esaki diode with degenerately doped pn junction can provide multiple switching behavior having multi-peak and valley currents. These multiple NDR characteristics can be controlled by doping concentration of tunnel diode and threshold voltage of NW transistor. By designing our NDR device, PVCR can be over $10^4$ at low operation voltage of 0.5 V in a single peak and valley current.

• Bulletin of the Korean Chemical Society
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• v.35 no.8
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• pp.2415-2418
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• 2014

In this report, the contact resistance between "electrode" and "lead" is investigated for reasonable measurements of samples' resistance in a polypyrrole (PPy) nanowire device. The sample's resistance, including "electrode-lead" contact resistance, shows a decrease as force applied to the interface increases. Moreover, the sample's resistance becomes reasonably similar to, or lower than, values calculated by resistivity of PPy reported in previous studies. The decrease of electrode-lead contact resistance by increasing the applying force was analyzed by using Holm theory: the general equation of relation between contact resistance ($R_H$) of two-metal thin films and contact force ($R_H{\propto}1/\sqrt{F}$). The present investigation can guide a reliable way to minimize electrode-lead contact resistance for reasonable characterization of nanomaterials in a microelectrode device; 80% of the maximum applying force to the junction without deformation of the apparatus shows reasonable values without experimental error.