• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2004년도 춘계학술대회 논문요약집
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• pp.148-148
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• 2004

전 세계적으로 컴퓨터 및 이동통신의 급속한 발전과 함께 전자, 통신부품을 비롯한 각종 부품들의 초소형화, 고기능화가 요구되고 있다. 이러한 추세에 따라 수 $\mu\textrm{m}$ 의 크기와 수 nm의 정밀도를 갖는 MEMS기술과 NANO 기술에 대한 연구가 활발히 전개되고 있다 MEMS 기술의 경우기존의 생산, 가공 공정과는 완전히 다른 반도체공정을 기반으로 한 리소그래피(lithography) 기술이나 전기도금(electroplating) 등의 기존 기계공학적 생산, 가공 방법을 넘어선 기술을 사용하게 되며 NANO 기술 역시 분자, 원자 단위를 기초로 한 AFM(atomic force microscope) 기술과 임프린팅(nanoimprinting) 기술 등의 새로운 기술을 접목시키는 생산 방법을 사용한다.(중략)

• 한국재료학회지
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• 제15권9호
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• pp.589-593
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• 2005

Nanoimprinting lithography (NIL) is known as a suitable technique for fabricating nano and micro structures of high definition. Hot embossing is one of NIL techniques and can imprint on thin films and bulk polymers. Key issues of hot embossing are time and expense needed to produce a stamp withstanding a high temperature and pressure. Fabrication of a metal stamp such as an electroplated nickel is cost intensive and time consuming. A ceramic stamp made by silicon is easy to break when the pressure is applied. In this paper, a plastic stamp using a high temperature epoxy was fabricated and tested. The plastic stamp was relatively inexpensive, rapid to produce and durable enough to withstanding multiple hot embossing cycles. The merits of low viscosity epoxy solutions were a fast degassing and a rapid filling the microstructures. The hot embossing process with plastic stamp was performed on PMMA substrates. The hot embossing was conducted at 12.6 bar, $120^{\circ}C$ and 10 minutes. An imprinted PMMA wafer was almost same value of the plastic stamp after 10 times embossing. Entire fabrication process from silicon master to plastic stamp was completed within 12 hours.

• 한국재료학회지
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• 제15권11호
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• pp.705-710
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• 2005

NIL (nanoimprint lithography) technique has demonstrated a high potential for wafer size definition of nanometer as well as micrometer size patterns. During the replication process by NIL, the stiction between the stamp and the polymer is one of major problems. This stiction problem is moi·e important in small sized patterns. An antistiction layer prevents this stiction ana insures a clean demolding process. In this paper, we were using a TCP (transfer coupled plasma) equipment and $C_4F_8$ as a precursor to make a Teflon-like antistiction layer. This antistiction layer was deposited on a 6 inch silicon wafer to have nanometer scale thicknesses. The thickness of deposited antistiction layer was measured by ellipsometry. To optimize the process factor such as table height (TH), substrate temperature (ST), working pressure (WP) and plasma power (PP), we were using a design of experimental (DOE) method. The table of full factorial arrays was set by the 4 factors and 2 levels. Using this table, experiments were organized to achieve 2 responses such as deposition rate and non-uniformity. It was investigated that the main effects and interaction effects between parameters. Deposition rate was in proportion to table height, working pressure and plasma power. Non-uniformity was in proportion to substrate temperature and working pressure. Using a response optimization, we were able to get the optimized deposition condition at desired deposition rate and an experimental deposition rate showed similar results.