• Title/Summary/Keyword: Nano-Electronics

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The characteristics of bismuth magnesium niobate multi layers deposited by sputtering at room temperature for appling to embedded capacitor (임베디드 커패시터로의 응용을 위해 상온에서 RF 스퍼터링법에 의한 증착된 bismuth magnesium niobate 다층 박막의 특성평가)

  • Ahn, Jun-Ku;Cho, Hyun-Jin;Ryu, Taek-Hee;Park, Kyung-Woo;Cuong, Nguyen Duy;Hur, Sung-Gi;Seong, Nak-Jin;Yoon, Soon-Gil
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.62-62
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    • 2008
  • As micro-system move toward higher speed and miniaturization, requirements for embedding the passive components into printed circuit boards (PCBs) grow consistently. They should be fabricated in smaller size with maintaining and even improving the overall performance. Miniaturization potential steps from the replacement of surface-mount components and the subsequent reduction of the required wiring-board real estate. Among the embedded passive components, capacitors are most widely studied because they are the major components in terms of size and number. Embedding of passive components such as capacitors into polymer-based PCB is becoming an important strategy for electronics miniaturization, device reliability, and manufacturing cost reduction Now days, the dielectric films deposited directly on the polymer substrate are also studied widely. The processing temperature below $200^{\circ}C$ is required for polymer substrates. For a low temperature deposition, bismuth-based pyrochlore materials are known as promising candidate for capacitor $B_2Mg_{2/3}Nb_{4/3}O_7$ ($B_2MN$) multi layers were deposited on Pt/$TiO_2/SiO_2$/Si substrates by radio frequency magnetron sputtering system at room temperature. The physical and structural properties of them are investigated by SEM, AFM, TEM, XPS. The dielectric properties of MIM structured capacitors were evaluated by impedance analyzer (Agilent HP4194A). The leakage current characteristics of MIM structured capacitor were measured by semiconductor parameter analysis (Agilent HP4145B). 200 nm-thick $B_2MN$ muti layer were deposited at room temperature had capacitance density about $1{\mu}F/cm^2$ at 100kHz, dissipation factor of < 1% and dielectric constant of > 100 at 100kHz.

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Liquid Crystal Driving of Transparent Electrode-Alignment Layer Multifunctional Thin Film by Nano-Wrinkle Imprinting of PEDOT:PSS/MWNT Nanocomposite (PEDOT:PSS/MWNT 나노복합체의 나노주름 임프린팅을 통한 투명전극-배향막 복합 기능 박막의 액정 구동)

  • Jong In Jang;Hae-Chang Jeong
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.16 no.1
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    • pp.8-17
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    • 2023
  • In conventional liquid crystal display(LCD) manufacturing process, Indium Tin Oxide(ITO) as transparent electrode and rubbing process of polyimide as alignment layer are essential process to apply electric field and align liquid crystal molecules. However, there are some limits that deposition of ITO requires high vacuum state, and rubbing process might damage the device with tribolectric discharge. In this paper, we made nanocomposite with PEDOT:PSS and MWNT to replace ITO and constructed alignment layer by nano imprint lithography with nano wrinkle pattern, to replace rubbing process. These replacement made that only one PEDOT:PSS/MWNT film can function as two layers of ITO and polyimide alignment layer, which means simplification of process. Transferred nano wrinkle patterns functioned well as alignment layer, and we found out lowered threshold voltage and shortened response time as MWNT content increase, which is related to increment of electric conductivity of the film. Through this study, it may able to contribute to process simplification, reducing process cost, and suggesting a solution to disadvantage of rubbing process.

Influence of metal annealing deposited on oxide layer

  • Kim, Eung-Soo;Cho, Won-Ju;Kwon, Hyuk-Choon;Kang, Shin-Won
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.365-368
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    • 2002
  • We investigated the influence of RTP annealing of multi-layered metal films deposited on oxides layer. Two types of oxides, BPSG and P-7205, were used as a bottom layer under multi-layered metal film. The bonding was not good in metal/BPSG/Si samples because adhesion between metal layer and BPSG oxide layer was poor by interfacial reaction during RTP annealing above 650$^{\circ}C$. On the other hand bonding was always good in metal/ P-TEOS /Si samples regardless of annealing temperature. We observed the interface between oxide and metal layers using AES and TEM. The phosphorus and oxygen profile in interface between metal and oxide layers were different in metal/BPSG/Si and metal/P-TEOS/Si samples. We have known that the properties of interface was improved in metal/BPSG/Si samples when the sample was annealed below 650$^{\circ}C$.

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Effects of oxygen partial pressure on electrical properties of transparent semiconducting indium zinc tin oxide thin films (IZTO 투명 반도체 박막의 전기적 특성에 대한 산소분압의 영향)

  • Lee, Keun-Young;Shin, Han-Jae;Han, Dong-Cheul;Kim, Sang-Woo;Lee, Do-Kyung
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.93-94
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    • 2009
  • The influences of $O_2$ partial pressure on electrical properties of transparent semiconducting indium zinc tin oxide thin films deposited at room temperature by magnetron sputtering have been investigated. The experimental results show that by varying the $O_2$ partial pressure during deposition, electron mobilities of IZTO thin film can be controlled between 7 and $25\;cm^2/Vs$. For conducting films, the carrier concentration and resistivity are ${\sim}\;10^{21}\;cm^{-3}$ and ${\sim}\;10^{-4}\;{\Omega}\;cm$, respectively. Concerning semiconducting films, under 12% $O_2$ partial fraction, the electron concentration is $10^{18}\;cm^{-3}$, showing the promising candidate for the application of transparent thin film transistors.

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50nm thick as-deposited poly silicon as an active layer of TFT for driving AM-OLEDs prepared at low temperature $(<200^{\circ}C)$ using Cat-CVD

  • Cho, Chul-Lae;Lee, Sung-Hyun;Lee, Chang-Hoon;Lee, Dea-Hyun;Lee, Sang-Yoon;Kwon, Jang-Yeon;Park, Kyung-Bae;Kim, Jong-Man;Jung, Ji-Sim;Hong, Wan-Shick
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.495-498
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    • 2006
  • The influence of various process parameters for the as-deposited poly silicon was investigated. The polycrystalline silicon films were successfully deposited on glass substrates at a low-temperature $(<200^{\circ}C)$ using the catalytic chemical vapor deposition (Cat-CVD). We achieved a low hydrogen content $({\sim}0.9%)$ and a high deposition rate $({\sim}35{\AA}/sec)$. The film is applicable to thin film transistors on plastic substrates.

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Removal of Photoresist Mask after the Cl2/HBr/CF4 Reactive Ion Silicon Etching (Cl2/HBr/CF4 반응성 이온 실리콘 식각 후 감광막 마스크 제거)

  • Ha, Tae-Kyung;Woo, Jong-Chang;Kim, Gwan-Ha;Kim, Chang-Il
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.23 no.5
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    • pp.353-357
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    • 2010
  • Recently, silicon etching have received much attention for display industry, nano imprint technology, silicon photonics, and MEMS application. After the etching process, removing of etch mask and residue of sidewall is very important. The investigation of the etched mask removing was carried out by using the ashing, HF dipping and acid cleaning process. Experiment shows that oxygen component of reactive gas and photoresist react with silicon and converting them into the mask fence. It is very difficult to remove by using ashing or acid cleaning process because mask fence consisted of Si and O compounds. However, dilute HF dipping is very effective process for SiOx layer removing. Finally, we found optimized condition for etched mask removing.

Fabrication and Characteristics of MOSFET Protein Sensor Using Nano SAMs (자기조립 단분자막을 이용한 MOSFET형 단백질 센서의 제작 및 특성)

  • Han, Seung-Woo;Park, Keun-Yong;Kim, Min-Suk;Kim, Hong-Seok;Bae, Young-Seuk;Choi, Sie-Young
    • Journal of Sensor Science and Technology
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    • v.13 no.2
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    • pp.90-95
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    • 2004
  • Protein and gene detection have been growing importance in medical diagnostics. Field effect transistor (FET) - type biosensors have many advantages such as miniaturization, standardization, and mass-production. In this work, we have fabricated metal-oxide-semiconductor (MOS) FET that operates as molecular recognitions based electronic sensor. Measurements were taken with the devices under phosphate buffered saline solution. The drain current ($I_{D}$) was decreased after forming self-assembled mono-layers (SAMs) used to capture the protein, which resulted from the negative charges of SAMs, and increased after forming protein by 11.5% at $V_{G}$ = 0 V due to the positive charges of protein.

Terabit-per-square-inch Phase-change Recording on Ge-Sb-Te Media with Protective Overcoatings

  • Shin Jin-Koog;Lee Churl Seung;Suh Moon-Suk;Lee Kyoung-Il
    • 정보저장시스템학회:학술대회논문집
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    • 2005.10a
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    • pp.185-189
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    • 2005
  • We reported here nano-scale electrical phase-change recording in amorphous $Ge_2Sb_2Te_5$ media using an atomic force microscope (AFM) having conducting probes. In recording process, a pulse voltage is applied to the conductive probe that touches the media surface to change locally the electrical resistivity of a film. However, in contact operation, tip/media wear and contamination could major obstacles, which degraded SNR, reproducibility, and lifetime. In order to overcome tip/media wear and contamination in contact mode operation, we adopted the W incorporated diamond-like carbon (W-DLC) films as a protective layer. Optimized mutilayer media were prepared by a hybrid deposition system of PECVD and RF magnetron sputtering. When suitable electrical pulses were applied to media through the conducting probe, it was observed that data bits as small as 25 nm in diameter have been written and read with good reproducibility, which corresponds to a data density of $1 Tbit/inch^2$. We concluded that stable electrical phase-change recording was possible mainly due to W-DLC layer, which played a role not only capping layer but also resistive layer.

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Long range-based low-power wireless sensor node

  • Komal Devi;Rita Mahajan;Deepak Bagai
    • ETRI Journal
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    • v.45 no.4
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    • pp.570-580
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    • 2023
  • Sensor nodes are the most significant part of a wireless sensor network that offers a powerful combination of sensing, processing, and communication. One major challenge while designing a sensor node is power consumption, as sensor nodes are generally battery-operated. In this study, we proposed the design of a low-power, long range-based wireless sensor node with flexibility, a compact size, and energy efficiency. Furthermore, we improved power performance by adopting an efficient hardware design and proper component selection. The Nano Power Timer Integrated Circuit is used for power management, as it consumes nanoamps of current, resulting in improved battery life. The proposed design achieves an off-time current of 38.17309 nA, which is tiny compared with the design discussed in the existing literature. Battery life is estimated for spreading factors (SFs), ranging from SF7 to SF12. The achieved battery life is 2.54 years for SF12 and 3.94 years for SF7. We present the analysis of current consumption and battery life. Sensor data, received signal strength indicator, and signal-to-noise ratio are visualized using the ThingSpeak network.