• Journal of Advanced Navigation Technology
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• v.20 no.1
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• pp.65-71
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• 2016

Quantum-dot cellular automata (QCA) consists of nano-scale cells and demands very low power consumption so that it is one of the alternative technologies that can overcome the limits of scaling CMOS technologies. Typical BCD-EXCESS 3 code converters using QCA have not considered the scalability so that the architectures are not suitable for a large scale circuit design. Thus, we design a BCD-EXCESS 3 code converter with scalability using QCADesigner and verify the effectiveness by simulation. Our structure have reduced 32 gates and 7% of garbage space rate compare with typical URG BCD-EXCESS 3 code converter. Also, 1 clock is only needed for circuit expansion of our structure though typical QCA BCD-EXCESS 3 code converter demands 7 clocks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.94-99
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• 2010

This paper presents a design procedure of digitally controlled oscillator(DCO) for power optimization. By controlling coarse tuning bits and fine tuning bits of DCO, the proposed design procedure can optimize the power dissipation and does not affect the LSB resolution, frequency range, linearity, portability. For optimization, the relationship between control bits and power dissipation of the DCO was analyzed. The DCO circuits using and unusing proposed design technique have been designed, simulated and proved using 0.13um, 1.2V CMOS library. The DCO circuit with proposed design technique has operation range between 283MHz and 1.1GHz and has 1.7ps LSB resolution and consumes 2.789mW at frequency of 1GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.28-33
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• 2008

This paper presents a continuous-time equalizer adopting a clock loss tracking technique for digital display interface. This technique uses bottom hold circuit to detect the incoming clock loss. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in $0.18{\mu}m$ CMOS technology. Experimental results summarize that eye-width of minimum 0.7UI is achieved until -33dB channel loss at 1.65Gbps. The average power consumption of the equalizer is a maximum 10mW, a very low value in comparison to those of previous researches, and the effective area is $0.127mm^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.99-100
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• 2006

Silicon-on-insulator(SOI) MOSFET with SiGe/Si heterostructure channel is an attractive device due to its potent use for relaxing several limits of CMOS scaling, as well as because of high electron and hole mobility and low power dissipation operation and compatibility with Si CMOS standard processing. SOI technology is known as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage roll-off issues in sub-deca nano-scale devices. For the forthcoming generations, the combination of SiGe heterostructures and SOI can be the optimum structure, so that we have developed SOI n-MOSFETs with SiGe/Si heterostructure channel grown by reduced pressure chemical vapor deposition. The SOI n-MOSFETs with a SiGe/Si heterostructure are presented and their DC characteristics are discussed in terms of device structure and fabrication technology.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.2
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• pp.227-236
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• 2017

Quantum-dot cellular automata(QCA) consists of nano-scale cells and demands very low power consumption so that it is one of the alternative technologies that can overcome the limits of scaling CMOS technologies. Various circuits on QCA have been researched until these days, a latch required for counter and state control has been proposed as a component of sequential logic circuits. A latch uses a feedback loop to maintain previous state. In QCA, a latch uses a square structure using 4 clocks for feedback loop. Previous latches have been proposed using many cells and clocks in coplanar. In this paper, in order to eliminate these defects, we propose a SR and D latch using multilayer structure on QCA. Proposed three dimensional loop structure is based on multilayer and consists of 3 layers. Each layer has 2 clock differences between layers in order to reduce interference. The proposed latches are analyzed and compared to previous designs.

• Advances in nano research
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• v.15 no.6
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• pp.521-531
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• 2023

Quantum-dot cellular automata (QCA) has shown great potential in the nanoscale regime as a replacement for CMOS technology. This work presents a specific approach to static random-access memory (SRAM) cell based on 2:1 multiplexer, 4-bit SRAM array, and 32-bit SRAM array in QCA. By utilizing the proposed SRAM array, a single-layer 16×32-bit SRAM with the read/write capability is presented using an optimized signal distribution network (SDN) crossover technique. In the present study, an extremely-optimized 2:1 multiplexer is proposed, which is used to implement an extremely-optimized SRAM cell. The results of simulation show the superiority of the proposed 2:1 multiplexer and SRAM cell. This study also provides a more efficient and accurate method for calculating QCA costs. The proposed extremely-optimized SRAM cell and SRAM arrays are advantageous in terms of complexity, delay, area, and QCA cost parameters in comparison with previous designs in QCA, CMOS, and FinFET technologies. Moreover, compared to previous designs in QCA and FinFET technologies, the proposed structure saves total energy consisting of overall energy consumption, switching energy dissipation, and leakage energy dissipation. The energy and structural analyses of the proposed scheme are performed in QCAPro and QCADesigner 2.0.3 tools. According to the simulation results and comparison with previous high-quality studies based on QCA and FinFET design approaches, the proposed SRAM reduces the overall energy consumption by 25%, occupies 33% smaller area, and requires 15% fewer cells. Moreover, the QCA cost is reduced by 35% compared to outstanding designs in the literature.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.1
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• pp.16-22
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• 2008

We fabricated thermally-evaporated 10 nm-Ni/30 nm and 70 nm Poly-Si/200 nm-$SiO_2/Si$ structures to investigate the thermal stability of nickel silicides formed by rapid thermal annealing(RTA) of the temperature of $300{\sim}1100^{\circ}C$ for 40 seconds. We employed for a four-point tester, field emission scanning electron microscope(FE-SEM), transmission electron microscope(TEM), high resolution X-ray diffraction(HRIXRD), and scanning probe microscope(SPM) in order to examine the sheet resistance, in-plane microstructure, cross-sectional microstructure evolution, phase transformation, and surface roughness, respectively. The silicide on 30 nm polysilicon substrate was stable at temperature up to $900^{\circ}C$, while the one on 70 nm substrate showed the conventional $NiSi_2$ transformation temperature of $700^{\circ}C$. The HRXRD result also supported the existence of NiSi-phase up to $900^{\circ}C$ for the Ni silicide on the 30 nm polysilicon substrate. FE-SEM and TEM confirmed that 40 nm thick uniform silicide layer and island-like agglomerated silicide phase of $1{\mu}m$ pitch without residual polysilicon were formed on 30 nm polysilicon substrate at $700^{\circ}C\;and\;1000^{\circ}C$, respectively. All silicides were nonuniform and formed on top of the residual polysilicon for 70 nm polysilicon substrates. Through SPM analysis, we confirmed the surface roughness was below 17 nm, which implied the advantage on FUSI gate of CMOS process. Our results imply that we may tune the thermal stability of nickel monosilicide by reducing the height of polysilicon gate.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.1
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• pp.125-133
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• 2010

A versatile micro-robotic platform for micro/nano scale assembly has been demanded in a variety of application areas such as micro-biology and nanotechnology. In the near future, a flexible and compact platform could be effectively used in a scanning electron microscope chamber. We are developing a platform that consists of miniature mobile robots and a compact positioning stage with multi degree-of-freedom. This paper presents the design and the implementation of a low-cost and compact multi degree of freedom position sensor that is capable of measuring absolute translational and rotational displacement. The proposed sensor is implemented by using a CMOS type image sensor and a target with specific hole patterns. Experimental design based on statistics was applied to finding optimal design of the target. Efficient algorithms for image processing and absolute position decoding are discussed. Simple calibration to eliminate the influence of inaccuracy of the fabricated target on the measuring performance also presented. The developed sensor was characterized by using a laser interferometer. It can be concluded that the sensor system has submicron resolution and accuracy of ${\pm}4{\mu}m$ over full travel range. The proposed vision-based sensor is cost-effective and used as a compact feedback device for implementation of a micro robotic platform.

• Journal of Sensor Science and Technology
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• v.23 no.2
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• pp.114-121
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• 2014

We report a polysilicon active area membrane field effect transistor (PSAFET) pressure sensor for low stress deflection of membrane. The PSAFET was produced in conventional FET semiconductor fabrication and backside wet etching. The PSAFET located at the front side measured pressure change using 300 nm thin-nitride membrane when a membrane was slightly strained by the small deflection of membrane shape from backside with any physical force. The PSAFET showed high sensitivity around threshold voltage, because threshold voltage variation was composed of fractional function form in sensitivity equation of current variation. When gate voltage was biased close to threshold voltage, a fractional function form had infinite value at $V_{tn}$, which increased the current variation of sensitivity. Threshold voltage effect was dominant right after the PSAFET was turned on. Narrow transistor channel established by small current flow was choked because electron could barely cross drain-source electrodes. When gate voltage was far from threshold voltage, threshold voltage effect converged to zero in fractional form of threshold voltage variations and drain current change was mostly determined by mobility changes. As the PSAFET fabrication was compatible with a polysilicon FET in CMOS fabrication, it could be adapted in low pressure sensor and bio molecular sensor.

• Journal of the Korean Vacuum Society
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• v.20 no.3
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• pp.182-188
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• 2011

Polysilazane and polymethylsilazane based precursor films were deposited on Si-substrate by spin-coating, subsequently annealed at $150{\sim}850^{\circ}C$, and characterized. Structural analysis, shrink, compositional change, etch rate, and gap-filling were observed. Annealing the precursor films led to formation of spin-on dielectric films. C-containing precursor films showed that less loss of N, H, and C while less gain of O than that of C-free precursor films at $400^{\circ}C$, but more loss of N, H, and C while more gain of O at $850^{\circ}C$. Thus polysilazane based precursor films exhibited less reduction in thickness of 14.5% than silazane based one of 15.6% at $400^{\circ}C$ but more 37.4% than 19.4% at $850^{\circ}C$. FTIR indicated that C induced smaller amount of Si-O bond, non-uniform property, and lower resistance to chemical etching.