• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.139-144
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• 2019

For recent decades, Non-volatile Memory (NVM) technologies have been drawing a high attention both in industry and academia due to its high density and short latency comparable to that of DRAM. However, NVM devices has write endurance problem and thus the current data structures that have been built around DRAM-specific features including unlimited program cycles is inadequate for NVM, reducing the device lifetime significantly. In this paper, we revisit a red-black tree extensively adopted for data indexing across a wide range of applications, and make it to better fit for NVM. Specifically, we observe that the conventional red-black tree wears out the specific location of memory because of its rebalancing operation to ensure fast access time over a whole dataset. However, this rebalancing operation frequently updates the long-lived nodes, which leads to the skewed wear out across the NVM cells. To resolve this problem, we present a new swapping wear-leveling red-black tree that periodically moves data in the worn-out node into the young node. The performance study with real-world traces demonstrates the proposed red-black tree reduces the standard deviation of the write count across nodes by up to 12.5%.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.181-186
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• 2015

With the rapid growth of semiconductor technologies, small-sized devices with powerful computing abilities are becoming a reality. As this environment has a limit on power supply, NVM storage that has a high density and low power consumption is preferred to HDD or SSD. However, legacy software layers optimized for HDDs should be revisited. Specifically, as storage performance approaches DRAM performance, existing I/O mechanisms and software configurations should be reassessed. This paper explores the challenges and implications of using NVM storage with a broad range of experiments. We measure the performance of a system with NVM storage emulated by DRAM with proper timing parameters and compare it with that of HDD storage environments under various configurations. Our experimental results show that even with storage as fast as DRAM, the performance gain is not large for read operations as current I/O mechanisms do a good job hiding the slow performance of HDD. To assess the potential benefit of fast storage media, we change various I/O configurations and perform experiments to quantify the effects of existing I/O mechanisms such as buffer caching, read-ahead, synchronous I/O, direct I/O, block I/O, and byte-addressable I/O on systems with NVM storage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.375-378
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• 2013

A reference voltage generator which is insensitive to PVT (process-voltage-temperature) variation necessary for NVM memory IPs such as EEPROM and MTP memories is designed in this paper. The designed BGR (bandgap reference voltage) circuit based on MagnaChip's $0.18{\mu}m$ EEPROM process uses a low-voltage bandgap reference voltage generator of cascode current-mirror type with a wide swing and shows a reference voltage characteristic insensitive to PVT variation. The minimum operating voltage is 1.43V and the VREF sensitivity against VDD variation is 0.064mV/V. Also, the VREF sensitivity against temperature variation is $20.5ppm/^{\circ}C$. The VREF voltage has a mean of 1.181V and its three sigma ($3{\sigma}$) value is 71.7mV.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.2
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• pp.61-66
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• 2023

As the use of smartphones expands to various areas and the level of multitasking increases, the support of swap is becoming increasingly important. However, swap support in smartphones is known to cause excessive storage traffic, resulting in memory thrashing. In this paper, we analyze how the thrashing of swaps that occurred in early smartphones has changed with the advancement of smartphone hardware. As a result of this analysis, we show that the swap thrashing problem can be resolved to some extent when the memory size increases. However, we also show that thrashing still occurs when the number of running apps continues to increase. Based on further analysis, we observe that this thrashing is caused by some hot data and suggest a way to solve this through an NVM-based architecture. Specifically, we show that a small size NVM with judicious management can resolve the performance degradation caused by smartphone swap.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.223-231
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• 2015

As smartphones support a variety of applications and their memory demand keeps increasing, the design of an efficient memory management policy is becoming increasingly important. Meanwhile, as nonvolatile memory (NVM) technologies such as PCM and STT-MRAM have emerged as new memory media of smartphones, characterizing memory references for NVM-based smartphone memory systems is needed. For the deep understanding of memory access features in smartphones, this paper performs comprehensive analysis of memory references for various smartphone applications. We first analyze the temporal locality and frequency of memory reference behaviors to quantify the effects of the two properties with respect to the re-reference likelihood of pages. We also analyze the skewed popularity of memory references and model it as a Zipf-like distribution. We expect that the result of this study will be a good guidance to design an efficient memory management policy for future smartphones.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.226-239
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• 2013

A number of systems have several on-chip memories with cache memory being one of them. Conventional cache memory consists of SRAM but the ratio of static energy to the total energy of the memory architecture becomes larger as the leakage power of traditional SRAM increases. Spin-Torque Transfer RAM (STT-RAM), which is a variety of Non-Volatile Memory (NVM), has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but it consumes too much writing energy. This study evaluated a wide range of energy consumptions of a two-level cache using NVM partially on a mobile processor. Through a number of experimental evaluations, it was confirmed that the use of NVM partially in the two-level cache effectively reduces energy consumption significantly.

• International journal of advanced smart convergence
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• v.12 no.1
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• pp.76-81
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• 2023

Journaling file systems are widely used to keep file systems in a consistent state against crash situations. As traditional journaling file systems are designed for block I/O devices like hard disks, they are not efficient for emerging byte-addressable NVM (non-volatile memory) media. In this article, we present a new in-memory journaling file system for NVM that is different from traditional journaling file systems in two respects. First, our file system journals only modified portions of metadata instead of whole blocks based on the byte-addressable I/O feature of NVM. Second, our file system bypasses the heavy software I/O stack while journaling by making use of an in-memory file system interface. Measurement studies using the IOzone benchmark show that the proposed file system performs 64.7% better than Ext4 on average.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.75-75
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• 2009

반도체 및 전자기기 산업에 있어 비활성메모리 (NVM)는 중요한 부운을 차지한다. NVM은 디스플레이 분야에 많은 기여를 하고 있으며, 특히 AMOLED에 적용이 가능하여 온도에 따라 변하는 구동 전류, 휘도, color balance에 따른 문제를 해결하는데 큰 역할을 한다. 본 연구는 NNN 구조에서 터널 층을 $SiN_X$ 박막에서 $SiO_XN_Y$ 박막으로 대체하기위한 $SiO_XN_Y$ 박막을 이용한 NNO구조의 NVM에 관한 연구이다. 이로 인하여 보다 얇으면서 우수한 절연 특성을 가지는 박막을 사용함으로써 실리콘 층으로부터 전하의 터널링 효과를 높여 전하 저장 정도를 높이고, 메모리 retention 특성을 향상시키는 터널 박막을 성장 시킬 수 있다. 최적의 NNO 구조의 메모리 소자를 제작하기 위하여 MIS 상태로 다양한 조건의 실험을 진행하였다. 처음으로 블로킹 박막의 두께를 조절하는 실험을 진행하여 최적 두께의 블로킹 박막을 찾았으며, 다음으로 전하 저장 박막의 band gap을 조절하여 최적의 band gap을 갖는 $SiN_X$ 박막을 찾았다. 마지막으로 최적두께의 $SiO_XN_Y$박막을 찾는 실험을 진행하였다. MIS 상태에서의 최적의 NNO 구조를 이용하여 유리 기판 상에 NNO 구조의 NVM 소자를 제작하였다. 제작된 메모리 소자는 문턱전압이 -1.48 V로 낮은 구동전압을 보였으며, I-V의 slope 값 역시 약 0.3 V/decade로 낮은 값을 보인다. 전류 점멸비($I_{ON}/I_{OFF}$)는 약 $5\times10^6$로 무수하였다. $SiN_X$의 band gap을 다양하게 조절하여 band gap 차이에 의한 밴드 저장 방식을 사용하였다. 또한 $SiN_X$은 전하를 전하 포획(trap) 방식으로 저장하기 때문에 본 연구에서의 메모리 소자는 밴드 저장 방식과 전하 포획 방식을 동시에 사용하여 우수한 메모리 특성을 갖게 될 것으로 기대된다. 우수한 비휘발성 메모리 소자를 제작하기 위해 메모리 특성에 많은 영향을 주는 터널 박막과 전하 저장 층을 다양화하여 소자를 제작하였다. 터널 박막은 터널링이 일어나기 쉽도록 최대한 얇으며, 전하 저장 층으로부터 기판으로 전하가 쉽게 빠져나오지 못하도록 절연 특성이 우수한 박막을 사용하였다. 전하 저장 층은 band gap이 작으며 trap 공간이 많은 박막을 사용하였다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.4
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• pp.15-20
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• 2016

Write amplification is a critical factor that limits the stable performance of flash-based storage systems. To reduce write amplification, this paper presents a new technique that cooperatively manages data in flash storage and nonvolatile memory (NVM). Our scheme basically considers NVM as the cache of flash storage, but allows the original data in flash storage to be invalidated if there is a cached copy in NVM, which can temporarily serve as the original data. This scheme eliminates the copy-out operation for a substantial number of cached data, thereby enhancing garbage collection efficiency. Experimental results show that the proposed scheme reduces the copy-out overhead of garbage collection by 51.4% and decreases the standard deviation of response time by 35.4% on average.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.7
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• pp.394-399
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• 2016

The silicon dioxide ($SiO_2$) was deposited using various gas as oxygen and nitrous oxide ($N_2O$) in nowadays. In order to improve electrical characteristics and the interface state density ($D_{it}$) in low temperature, It was deposited with carbon dioxide ($CO_2$) and silane ($SiH_4$) gas by inductively coupled plasma chemical vapor deposition (ICP-CVD). Each $D_{it}$ of $SiO_2$ using $CO_2$ and $N_2O$ gas was $1.30{\times}10^{10}cm^{-2}{\cdot}eV^{-1}$ and $3.31{\times}10^{10}cm^{-2}{\cdot}eV^{-1}$. It showed $SiO_2$ using $CO_2$ gas was about 2.55 times better than $N_2O$ gas. After 10 years when the thin film was applied to metal/insulator/semiconductor(MIS)-nonvolatile memory(NVM), MIS NVM using $SiO_2$($CO_2$) on tunneling layer had window memory of 2.16 V with 60% retention at bias voltage from +16 V to -19 V. However, MIS NVM applied $SiO_2$($N_2O$) to tunneling layer had 2.48 V with 61% retention at bias voltage from +20 V to -24 V. The results show $SiO_2$ using $CO_2$ decrease the $D_{it}$ and it improves the operating voltage.