• The Transactions of the Korean Institute of Power Electronics
• /
• v.13 no.1
• /
• pp.9-14
• /
• 2008

Since they use the low switching frequency in multilevel inverter systems, they generate the high low frequency harmonic components. Generally, LC filter is used at the output terminal of inverter systems to solve this problem. But it causes a voltage drop at the output terminal by use of damping resistors, and causes the problem in which system efficiency decreases due to power loss of the damping resistor. In this paper, we proposed an output filter design method for NPC three-level inverter systems with low switching frequency. And we analyzed the efficiency of the proposed filter system, and the effectiveness of the proposed system is verified by simulation and experimental results.

• Journal of the Semiconductor & Display Technology
• /
• v.14 no.4
• /
• pp.72-77
• /
• 2015

Three-level diode clamped multilevel inverter, generally known as neutral point clamped (NPC) inverter, has an inherent problem causing neutral point (NP) potential variation. Until now, the NP potential problem of variation has been investigated and lots of solutions have also been proposed. This paper presents a neutral point voltage control technology using the anti-windup PI controller and offset technology of PWM (Pulse Width Modulation) to control the variation of NPC 3-phase three-level inverter neutral point voltage. And the proposed algorithm is tested and verified using a PLL (Phase Locked Loop) in order to synchronize the phase voltage from the line voltage of grid. It significantly improves the voltage balancing under a solar fluctuation conditions of the inverter. Experimental results show the good performance and effectiveness of the proposed method.

• Proceedings of the KIPE Conference
• /
• 2013.07a
• /
• pp.45-46
• /
• 2013

멀티레벨 고압인버터 토폴로지 중 저압 Power Cell를 이용하여 고압을 출력하는 Cascaded 방식이 산업계에서는 널리 사용되고 이다. 최근 제품화된 Cascaded 방식은 크게 두 가지 형태로 구분할 수 있다. 저압 Power Cell에 단상 H-Bridge를 이용한 Cascaded H-Bridge 멀티레벨 인버터와 단상 NPC(Neutral Point Clamped) 토폴로지를 적용한 Cascaded NPC 멀티레벨 인버터이다. 이 중 Cascaded NPC 멀티레벨 인버터의 경우 적은 수의 셀을 사용하여 CHB와 동일한 출력 레벨을 생성할 수 있으며, NPC 방식의 고압 인버터 고유의 장점을 모두 구현할 수 있다. 반대로 CHB Type과 NPC type의 단점인 복잡한 구조의 Phase Shift Transformer와 DC_Link 중성점 전압이 변동하는 단점 또한 나타나게 된다. 본 논문에서는 Cascaded NPC 멀티레벨 인버터의 이러한 단점을 극복하기 위한 새로운 방식의 Phase Shift Transformer와 NPC Power Cell의 중성점 전압 변동을 줄일 수 있는 기법에 대해 설명하고 이 기법에 대한 타당성을 모의시험을 통해 검증하였다.

• Journal of Power Electronics
• /
• v.19 no.3
• /
• pp.727-743
• /
• 2019

This paper presents a pulse-width modulation strategy to eliminate the common mode voltage (CMV) with reduced CMV spikes in multilevel inverters since a high CMV magnitude and its fast variations dv/dt result in bearing failure of motors, overvoltage at motor terminals, and electromagnetic interference (EMI). The proposed method only utilizes the zero CMV states in a space vector diagram and it is implemented by a carrier-based pulse-width modulation (CBPWM) method. This method is generalized for odd number levels of inverters including neutral-point-clamped (NPC) and cascaded H-bridge inverters. Then it is extended to the over-modulation mode. The over-modulation mode is implemented by using the two-limit trajectory principle to maintain linear control and to avoid look-up tables. Even though the CMV is eliminated, CMV spikes that can cause EMI and bearing current problems still exist due to the deadtime effect. As a result, the deadtime effect is analyzed. By taking the deadtime effect into consideration, the proposed method is capable of reducing CMV spikes. Simulation and experimental results verify the effectiveness of the proposed strategy.

• Journal of Electrical Engineering and Technology
• /
• v.9 no.2
• /
• pp.489-500
• /
• 2014

This paper presents a simple modified unipolar carrier-based pulsewidth modulation (CB-PWM) strategy for the three-level neutral-point-clamped (NPC) voltage source inverter (VSI). Analytical expressions for the relationship between modulation reference signals and output voltages are derived. The proposed modulation technique for the three-level NPC VSI includes the maximum and minimum of the three-phase sinusoidal reference voltages with zero-sequence voltage injection concept. The proposed modified CB-PWM strategy incorporates a novel method that requires only of one triangular carrier wave for generate the gating pulses in three-level NPC VSI. It has the advantages of being simplifying the algorithm with no need of complex two/multi-carrier pulsewidth modulation or space vector modulation (SVM) and it's also simple to implement. The possibility of the proposed CB-PWM technique has been verified though computer simulation and experimental results.

• Proceedings of the KIPE Conference
• /
• 2007.07a
• /
• pp.101-103
• /
• 2007

Since they use the low switching frequency in multilevel inverter systems, they generate the high low frequency harmonic components. Generally, LC filter is used at the output terminal of inverter systems to solve this problem. But it causes a voltage drop at the output terminal by use of damping resistors, and causes the problem in which system efficiency decreases due to power loss of the damping resistor. In this paper, we proposed an output filter design method for NPC three-level inverter systems with low switching frequency. And we analyzed the efficiency of the proposed filter system, and the effectiveness of the proposed system is verified by simulation and experimental results.

• Proceedings of the KIPE Conference
• /
• 2001.10a
• /
• pp.369-373
• /
• 2001

Multilevel inverter has attracted great interest in high-voltage high-power field because of its less distorted output. In this paper, a direct torque control (DTC) technique based on a three-level neutral-point-clamped (NPC) inverter is presented. In order to solve the intrinsic neutral-point voltage-balancing problem and to obtain a high performance DTC, a special vector selection method is introduced and the concept of virtual vector is developed. By using the proposed PWM strategy, a MRAS speed sensor-less DTC drive can be achieved without sensing the neutral-point voltage, The strategy can be verified by simulation and experimental results.

• Journal of Power Electronics
• /
• v.19 no.4
• /
• pp.907-921
• /
• 2019

This paper presents two advanced hybrid pulse-width modulation (PWM) strategies for multilevel inverters (MLIs) that provide both common-mode voltage (CMV) elimination and current ripple reduction. The first PWM utilizes sequences that apply one switching state at the double ends of a half-carrier cycle. The second PWM combines the advantages of the former and an existing four-state PWM. Analyses of the harmonic characteristics of the two groups of switching sequences based on a general switching voltage model are carried out, and algorithms to optimize the current ripple are proposed. These methods are simple and can be implemented online for general n-level inverters. Using a three-level NPC inverter and a five-level CHB inverter, good performances in terms of the root mean square current ripple are obtained with the proposed PWM schemes as indicated through improved harmonic distortion factors when compared to existing schemes in almost the entire region of the modulation index. This also leads to a significant reduction in the current total harmonic distortion. Simulation and experimental results are provided to verify the effectiveness of the proposed PWM methods.

• Proceedings of the KIPE Conference
• /
• 2003.07b
• /
• pp.625-629
• /
• 2003

멀티 레벨 인버터는 고 전력 시스템에서 많이 사용되고 있다. 일반적으로 멀티 레벨 인버터는 캐스케이드와 NPC(Nuetral Point clamped) 두 가지 회로 방식이 있다. 동일한 시스템 조건에서 두 인버터를 비교하여 어느 한 인버터의 특성이 좋은가를 분석하기 위해 동일 조건하에 인버터 구조에 따라서 회로방식이 THD에 어떠한 영향을 주는지에 대해서 시뮬레이션을 통하여 살펴보고, FMI(Fundamental Modulation Index, 기본파 변조 지수)에 따라 두 회로 방식에 대한 THD 변화를 레벨 수에 따라 분석하고자 한다. 인버터에 사용되는 PWM 방식으로는 멀티 캐리어 PWM을 사용하였다.

• Proceedings of the KIPE Conference
• /
• 2012.07a
• /
• pp.510-511
• /
• 2012

최근 전력변환 분야에서 고압 인버터의 요구가 증가함에 따라 국내외 Drive 업체에서 멀티레벨 인버터에 대한 관심이 커지고 있다. 특히, 현재 LS산전에서 양산되고 있는 Cascaded H-Bridge(이하 CHB) Type의 멀티레벨 인버터와 더불어 1981년 Nabae 교수에 의해 처음 제안된 3-Level Neutral Point Clamped(이하 NPC) Type의 멀티레벨 인버터는 최근 그 성능 및 신뢰성에 대한 검증이 많이 이루어 졌으며 경쟁사인 ABB/YASKAWA/TMEIC사(社) 등에서 실제 제품화가 되고 있다. 본 논문에서는 현재 LS산전에서 개발중인 3-Level NPC 인버터 기반의 5-Level NPC 인버터의 System 최적화를 위해 양산중인 CHB Type의 멀티레벨 인버터와 그 특성을 비교하여 해당 인버터 개발에 대한 타당성을 검증하였다.