• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.2
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• pp.81-89
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• 2015

In this paper, we proposed a new matrix transposition scheme, called asymmetry sub-matrix, and conducted the in-depth performance evaluation of the proposed scheme with other prior schemes, including element-major, row-major and sub-matrix schemes in large-scale matrix. In our results, the proposed asymmetry sub-matrix scheme shows the best performance compared to other prior schemes, while sub-matrix scheme shows the second best performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.26-27
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• 2006

To develop tera-bit level SONOS flash memories, SONOS unit memory and 64 bit flash arrays are fabricated. The unit cells have both channel length and width of 30nm. The NAND & NOR arrays are fabricated on SOI wafer and patterned by E-beam. The unit cells represent good write/erase characteristics and reliability characteristics. SSL-NOR array have normal write/erase operation. These researches are leading the realization of Tera-bit level non-volatile nano flash memory.

• Journal of the Semiconductor & Display Technology
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• v.18 no.2
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• pp.82-86
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• 2019

The reliability of 3D NAND flash memory cell is affected by the charge migration which can be divided into the vertical migration and the lateral migration. To clarify the difference of two migrations, the activation energy of the charge loss is extracted and compared in a conventional square device pattern and a new test pattern where the perimeter of the gate is exaggerated but the area is same. The charge loss is larger in the suggested test pattern and the activation energy is extracted to be 0.058 eV while the activation energy is 0.28 eV in the square pattern.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.77-78
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• 2009

In this paper, we study a pattern-aware write cache policy using a NAND flash memory in disk-based mobile storage systems. Our work is designed to face a mix of a number of sequential accesses and fewer non-sequential ones in mobile storage systems by redirecting the latter to a NAND flash memory and the former to a disk. Experimental results show that our policy improves the overall I/O performance by reducing the overhead significantly from a non-volatile cache over a traditional one.

• Journal of KIISE
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• v.43 no.4
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• pp.411-418
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• 2016

In recent times, NAND flash memory has become widely used as secondary storage for computing devices. Accordingly, to take advantage of NAND flash memory, new file systems have been actively studied and proposed. The performance of these file systems is generally measured with benchmark tools. However, since benchmark tools are executed by software simulation methods, many researchers get non-uniform benchmark results depending on the system environments. In this paper, we use Filebench, one of the most popular and representative benchmark tools, to analyze benchmark results and study the reasons why the benchmark result variations occur. Our experimental results show the differences in benchmark results depending on the system environments. In addition, this study substantiates the fact that system performance is affected mainly by background I/O requests and fsync operations.

• Journal of Digital Convergence
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• v.20 no.5
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• pp.593-598
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• 2022

Recently, data production has seen explosive growth, and the storage systems to store these big data safely and quickly is evolving in various ways. A typical configuration of storage systems is the use of SSDs with fast data processing speed as a RAID group that can maintain reliable data. However, since NAND flash memory, which composes SSD, has the feature that deterioration if writes more than a certain number of times are repeated, can increase the likelihood of simultaneous failure on multiple SSDs in a RAID group. And this can result in serious reliability problems that data cannot be recovered. Thus, in order to solve this problem, we propose a method of throttling IOs so that each SSD within a RAID group leads to a different life-end. The technique proposed in this paper utilizes SMART to control the state of each SSD and the number of IOs allocated according to the data pattern used step by step. In addition, this method has the advantage of preventing large amounts of concurrency defects in RAID because it induces differential lifetime finishes of SSDs.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.07a
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• pp.231-234
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• 2014

플래시 메모리는 빠른 처리 속도, 비 휘발성, 저 전력, 강한 내구성 등으로 인해 최근 여러 분야에서 활용도가 증가하고 있다. 또한, 최근 비트 당 가격이 저렴해지면서 NAND 플래시 기반의 SSD (Solid State Disk)가 기존 기계적 메커니즘의 HDD(Hard Disk Drive)를 대체할 새로운 저장 장치로 주목받고 있다. 이 논문에서는 SSD 설계에서 고려해야 할 사항들을 정리하였으며, SSD의 성능향상을 위해 설계 고려사항들에 대한 해결방안을 위한 연구방향을 제시한다.

• Journal of Internet of Things and Convergence
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• v.9 no.4
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• pp.9-14
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• 2023

Recently, resource optimization research has been actively conducted in enterprises and data centers to manage the rapid growth of big data. In particular, thin provisioning, which allocates a large number of resources compared to fixedly allocated storage resources, has the effect of reducing initial costs, but as the number of resources actually used increases, the cost effectiveness decreases and the management cost for allocating resources increases. In this paper, we propose a technique that divides the physical blocks of flash memory into single-bit cells and multi-bit cells, formats them with a hybrid technique, and manages them by dividing frequently used hot data and infrequently used cold data. The proposed technique has the advantage that the physical and allocated resources are the same, such as thick provisioning, and can be used without additional cost increase, and the underutilized resources can be managed in multi-bit cell blocks, such as thin provisioning, which can allocate more resources than typical storage devices. Finally, we estimated the resource optimization effectiveness of the proposed technique through experiments based on simulations.

• The Journal of the Korea Contents Association
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• v.16 no.3
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• pp.91-101
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• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.6
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• pp.1299-1306
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• 2023

In this paper, we present a system for undesignated cultural heritage management and real-time theft chase, which uses flash-based large-capacity storage. The proposed system is composed of 3 parts, such as a cultural management device, a flash-based server, and a monitoring service for managing cultural heritages and chasing thefts using IoT technologies. However flash-based storage needs methods to overcome the limited lifespan. Therefore, in this paper, we present a system, which uses the disk buffer in flash-based storage to overcome the disadvantage, and evaluate the system performance in various environments. In our experiments, LRU policy shows the number of direct writes in the flash-based storage by 10.7% on average compared with CLOCK and FCFS.