• Title/Summary/Keyword: N-Buffer Layer

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Enhanced Performance of the OLED with Plasma Treated ITO and Plasma Polymerized Methyl Methacrylate Buffer Layer (ITO 플라즈마 표면처리와 ppMMA 버퍼층으로 제작한 OLED의 발광특성)

  • Lim Jae-Sung;Shin Paik-Kvun
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.55 no.1
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    • pp.30-33
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    • 2006
  • Transparent indium tin oxide (ITO) anode surface was modified using $O_3$ Plasma and organic ultrathin buffer layers were deposited on the ITO surface using 13.56 MHz RF plasma polymerization technique. The EL efficiency, operating voltage and lifetime of the organic light-emitting device (OLED) were investigated in order to study the effect of the plasma surface treatment and role of plasma polymerized organic ultrathin buffer layer. Poly methylmethacrylate (PMMA) layers were plasma polymerized on the ITO anode as buffer layer between anode and hole transport layer (HTL). The plasma polymerization of the organic ultrathin layer were carried out at a homemade capacitive-coupled RF plasma equipment. N,N'-diphenyl-N,N'(3- methylphenyl)-1,1'-diphenyl-4,4'-diamine (TPD) as HTL, Tris(8-hydroxyquinolinato) Aluminum $(Alq_3)$ as both emitting layer (EML)/electron transport layer (ETL), and aluminum layer as cathode were deposited using thermal evaporation technique. Effects of the plasma surface treatment of ITO and plasma polymerized buffer layers on the OLED performance were discussed.

Effects of Brazing Processing Condition on Mechanical Properties and Reliability of Si3N/S.S. 316 Joints (브레이징 접합공정 조건이 SiN4/S.S. 316 접합체의 기계적 특성 및 신뢰도에 미치는 영향)

  • Chang, Hwi-Souck;Park, Sang-Whan;Choi, Sung-Churl
    • Journal of the Korean Ceramic Society
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    • v.39 no.10
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    • pp.955-962
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    • 2002
  • The microstructure change of brazed $Si_3N_4$/Stainless steel 316 joint with Cu buffer layer were examined to clarify the effects of brazing process conditions such as brazing time and temperature on the mechanical properties and reliability of brazed joints. For the brazed joint above 900${\circ}C$, the Cu buffer layer was completely dissolved into brazing alloy and the thickness of reaction product formed at $Si_3N_4$/brazing alloy joint interface was abruptly increased, which could increase the amounts of residual stress developed in the joint. The fracture strength of brazed $Si_3N_4$/Stainless steel 316 joint with Cu buffer layer at 950${\circ}C$ was much reduced comparing to those of joints brazed at the lower temperature. But, it was found that the effects of brazing time was not critical on the mechanical properties as well as the reliability of $Si_3N_4$/Stainless steel 316 joint with Cu buffer layer brazed at the temperature below 900${\circ}C$.

박막태양전지 TCO/P 버퍼층 활성화를 위한 P-layer 최적화 Simulation

  • Jang, Ju-Yeon;Baek, Seung-Sin;Kim, Hyeon-Yeop;Lee, Jun-Sin
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.91-91
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    • 2011
  • 박막태양전지의 높은 효율개선을 위해 TCO층과 p-layer 사이에 buffer layer를 넣어 Voc와 FF를 개선하는 연구가 진행되고 있다. 이에 buffer layer의 활성화 정도를 높이기 위해 p-layer을 최적화 시키고자한다. 이 실험에서 a-Si:B에 N2O를 도핑시켜 Bandgap Energy 2.0 eV, Activation Energy 0.4 eV인 a-SiOx:B 막을 제작하여 buffer layer로 사용하였고 이 buffer layer에 의한 cell의 효율 향상을 최적화 하기위해 ASA simulation을 이용해 p-layer의 Bandgap Energy와 Activation Energy를 가변 하여 보았다. 실험결과 p-layer의 Bandgap Energy 1.95 eV에서 buffer layer와 p-layer사이에서의 barrier가 최소가 됨을 확인 할 수 있었고 Actication Energy 0.5 eV에서 가장 높은 Voc를 가짐을 알 수 있었다. 본 연구를 통해 p-layer의 Bandgap Energy 1.95 eV, Activation Energy 0.5 eV에서 buffer layer를 활성화시키기 위한 p-layer의 최적화 조건을 구현해 볼 수 있었다.

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Surface Analysis of Plasma Pretreated Sapphire Substrate for Aluminum Nitride Buffer Layer

  • Jeong, Woo Seop;Kim, Dae-Sik;Cho, Seung Hee;Kim, Chul;Jhin, Junggeun;Byun, Dongjin
    • Korean Journal of Materials Research
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    • v.27 no.12
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    • pp.699-704
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    • 2017
  • Recently, the use of an aluminum nitride(AlN) buffer layer has been actively studied for fabricating a high quality gallium nitride(GaN) template for high efficiency Light Emitting Diode(LED) production. We confirmed that AlN deposition after $N_2$ plasma treatment of the substrate has a positive influence on GaN epitaxial growth. In this study, $N_2$ plasma treatment was performed on a commercial patterned sapphire substrate by RF magnetron sputtering equipment. GaN was grown by metal organic chemical vapor deposition(MOCVD). The surface treated with $N_2$ plasma was analyzed by x-ray photoelectron spectroscopy(XPS) to determine the binding energy. The XPS results indicated the surface was changed from $Al_2O_3$ to AlN and AlON, and we confirmed that the thickness of the pretreated layer was about 1 nm using high resolution transmission electron microscopy(HR-TEM). The AlN buffer layer deposited on the grown pretreated layer had lower crystallinity than the as-treated PSS. Therefore, the surface $N_2$ plasma treatment on PSS resulted in a reduction in the crystallinity of the AlN buffer layer, which can improve the epitaxial growth quality of the GaN template.

Investigation on the Growth of Tungsten Carbide Layer as a Buffer for GaN-on-Si Technology (GaN-on-Si 기술을 위한 탄화텅스텐 버퍼층의 성장에 관한 연구)

  • Cho, Sungmin;Choi, Junghoon;Choi, Sungkuk;Cho, Youngji;Lee, Seokhawn;Chang, Jiho
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.30 no.1
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    • pp.1-6
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    • 2017
  • Tungsten carbide (WC) has been suggested as a new buffer layer for the GaN-on-Si technology. We have investigated and optimized the sputtering condition of WC layer on the Si-substrate. We confirmed the suppression of the Si melt-back phenomenon. In addition, surface energy of WC/Si layer was measured to confirm the possibility as a buffer layer for GaN growth. We found that the surface energy(${\gamma}=82.46mJ/cm^2$) of WC layer is very similar to that of sapphire substrate(${\gamma}=82.71mJ/cm^2$). We grow GaN layer on the WC buffer by using gas-source MBE, and confirm that it is available to grow a single crystalline GaN layer.

Effect of SiO2 Buffer Layer Thickness on the Device Reliability of the Amorphous InGaZnO Pseudo-MOS Field Effect Transistor (SiO2 완충층 두께에 따른 비정질 InGaZnO Pseudo-MOS Field Effect Transistor의 신뢰성 평가)

  • Lee, Se-Won;Hwang, Yeong-Hyeon;Cho, Won-Ju
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.1
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    • pp.24-28
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    • 2012
  • In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO ${\Psi}$-MOSFET) with a stacked $Si_3N_4/SiO_2$ (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a $SiO_2$ buffer layer. The roles of a $SiO_2$ buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and $Si_3N_4$. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick $SiO_2$ buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin $SiO_2$ buffer layer which highlighted bias and light-induced hole trapping into the $Si_3N_4$ layer. As a results, the pseudo-MOS transistor with a 20-nm-thick $SiO_2$ buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(${\mu}_{FE}$) of 12.3 $cm^2/V{\cdot}s$, subthreshold slope (SS) of 148 mV/dec, trap density ($N_t$) of $4.52{\times}1011\;cm^{-2}$, negative bias illumination stress (NBIS) ${\Delta}V_{th}$ of 1.23 V, and negative bias temperature illumination stress (NBTIS) ${\Delta}V_{th}$ of 2.06 V.

Characteristic Effects of Buffer Layers on Organic Light Emitting Devices

  • Park, Jae-Hoon;Lee, Yong-Soo;Kwak, Yun-Hee;Choi, Jong-Sun
    • KIEE International Transactions on Electrophysics and Applications
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    • v.11C no.3
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    • pp.43-48
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    • 2001
  • The stability and efficiency of organic light emitting devices are the most critical problems to be solved. The devices based on tris-8-(hydroxyquinoline) aluminum ($Alq_3$) and N,N-diphenyl-N,N-bis(3-methylphenyl)-1, 1-biphenyl-4,4-diamine (TPD) were used to study the effects of buffer layers on their characteristics. We have investigated the characteristic effects of CuPc (copper phthalocyanine) and pentacene buffer layers on the device characteristics, the (5${\sim}$20 nm thick) CuPc layers and the (10${\sim}$20 nm thick) pentacene layers were deposited. Efficiency was slightly improved and the turn-on voltages of the devices with the buffer layers were observed to have lower values than those of the devices without the buffer layers. It is believed that this result is attributed to the improvement of hole injection capability through the buffer layers into hole transport layer (HTL). We have also studied the atomic force microscopic images of the TPD layers deposited on the buffer layer and the bare ITO.

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Effect of 3C-SiC buffer layer on the characteristics of AlN films supttered on Si Substrates (3C-SiC 버퍼층이 Si 기판위에 스퍼터링된 AlN 막의 특성에 미치는 영향)

  • Ryu, Kyeong-Il;Chung, Gwiy-Sang
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.04b
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    • pp.3-6
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    • 2009
  • Aluminum nitride (AIN) thin films were deposited on a polycrystalline 3C-SiC intermediate layer by a pulsed reactive magnetron sputtering system. Characteristics of the AIN/SiC heterostructures were investigated by field emission scanning electron microscopy (FE-SEM), atomic force microscopy (AFM), X-ray diffraction (XRD), and Fourier transform infrared spectroscopy (FT-IR). The columnar structure of AIN thin films was observed by FE-SEM. The surface roughness of AlN films on the 3C-SiC buffer layer was measured using AFM. The XRD pattern of AlN films on SiC buffer layers was highly oriented at (002). Full width at half maximum (FWHM) of the rocking curve near (002) reflections was $1.3^{\circ}$. The infrared absorbance spectrum indicated that the residual stress of AIN thin films grown on SiC buffer layers was nearly negligible. The 3C-SiC intermediate layers are promising for the realization of nitride based electronic and mechanical devices.

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Reduction of Drain Leakage Current by AlGaAs buffer layer in GaAs MESFET (GaAs MESFET에서 AlGaAs buffer layer에 의한 Drain 누설전류 차단)

  • Park, Jun;Jo, Jung-Yol
    • Proceedings of the KIEE Conference
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    • 1998.07d
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    • pp.1321-1323
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    • 1998
  • We investigated drain leakage current in GaAs power MESFET. The device we studied by 20 simulation has a $1000{\AA}$ thick AlGaAs buffer layer under n-GaAs active layer. The calculation shows that the leakage current through GaAs substrate is significantly reduced by the buffer layer.

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