• 전자공학회논문지B
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• 제33B권5호
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• pp.41-51
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• 1996

In this paper, anew parallel processing system based on a cluster architecture which provides scalability of a parallel processing system while maintains shared memory multiprocessor characteristics is proposed. In recent days low cost, high performnce microprocessors have led to construction of large scale parallel processing systems. Such parallel processing systems provides large scalability but are mainly used for scientific applications which have large data parallelism. A shared memory multiprocessor system like TICOM is currently used as aserver for the commercial application, however, the shared memory multiprocessor system is known to have very limited scalability. The proposed architecture can support scalability and performance of the parallel processing system while it provides adaptability for the commerical application, hence it can overcome the limitation of the shared memory multiprocessor. The architecture and characteristics of the proposed system shall be described. A proprietary hierarchical crsossbar network is designed for this system, of which the protocol, routing and switching technique and the signal transfer technique are optimized for the proposed architecture. The design trade-offs for the network are described in this paper and with simulation usihng the SES/workbench, it is explored that the network fits to the proposed architecture.

• 한국통신학회논문지
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• 제12권5호
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• pp.505-518
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• 1987

본 논문은 2레벨 및 3레벨 형태의 펄스폭변조 기법을 해석한 후 이런 두 형태의 펄스폭변조인버터에 대한 제어기로서 사용될 수 있는 다중 프로세서를 설계하였다. 설계된 다중 프로세서 방식은 Supervisory 프로세서가 공용메모리를 통해서 Local 프로세서와 상호 연결되어 있는 계층적인 구성을 도입함으로써 정교한 디지탈제어특성을 보였다. 이런 다중 프로세서 구성을 실현함으로써 시스템의 소프트웨어를 변경시 큰 자유도를 얻을 수 있었고 단일 프로세서구성때보다 소프트웨어를 더욱 간단하게 할 수 있었다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1986년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 17-18 Oct. 1986
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• pp.619-622
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• 1986

컴퓨터 기술의 발달에 따라 디지탈 전산기는 연산처리 능력이 더욱 빨라지고, 더욱 큰 기억용량을 갖게 되었다. 따라서 산업공정, 화학프랜트, 원자력발전 및 항공분야 등의 복잡한 연속 동특성계에 대한 실시간 시뮬레이션이 가능하게 되었다. 특히 복잡한 연속 동특성계의 시뮬레이션 목적으로 Multiprocessor 형태의 전산기가 개발되었다. 이 Multiprocessor형태의 전산기는 D/A 변환기와 A/D 변환기를 갖추므로써 실시간 실물 모의시험(A real time hardware-in-the-loop simulation) 시의 컴퓨터와 외부장비와의 데이타 전달이 용이하여 졌다. 본 연구에서는 비행체의 비행자세를 제어하기 위한 조종장치의 설계해석 및 성능시험을 위하여 Multiprocessor를 이용하여 실시간 실물 모의실험이 가능함을 보였다. 본 시뮬레이션에 사용된 전산기는 AD10 전산기이다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 16-17 Oct. 1987
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• pp.426-430
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• 1987

The reliability is the critical issue in many computer applications, particularly in process control system. In this paper we describe how to achieve the reliability improvement in controller system based multiprocessor. The proposed method is accomplished by using the techniques of fault detection, fault isolation, safe action, and fault diagnosis.

• 대한전자공학회논문지
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• 제24권5호
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• pp.777-785
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• 1987

In this paper, a tightly-coupled multiprocessor system is implemented with four processing elements based on MC68000 CPU, a common menory (128KB), and a single time-shared bus. The multi-tasking operating system, MTOS, is modified so that the multiprocessor system can support multitasking and multiprocessing. The performance of the proposed system is evaluated by stochastic Petri Net system modeling. The efficiency and the processing power are simulated for various load factors and up to 16 PEs. By running benchmark programs, such as quicksort, FFT, and matrix-multiplication, the speed of parallel processing is compared with that of a single processor.

• 한국정보과학회논문지:시스템및이론
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• 제34권4호
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• pp.145-157
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• 2007

단일 칩 다중 프로세서의 경우 표준화된 병렬 프로그래밍 방법이 없는데 OpenMP를 사용하면 병렬 프로그래밍이 쉬우므로 OpenMP는 단일 칩 다중 프로세서를 위한 매력적인 병렬 프로그래밍 모델이다. 그런데 단일 칩 다중 프로세서 시스템의 구조는 대상 응용 프로그램에 따라 다양할 수 있다. 따라서 각 시스템마다 다른 방식으로 OpenMP를 구현해야 할 필요가 있다. 본 논문에서는 운영체제를 사용하지 않는 단일 칩 다중 프로세서를 위한 OpenMP 구현과 주요 디렉티브의 효과적인 변환을 제안하여 특수한 하드웨어에 의존하지 않고 OpenMP 디렉티브의 추가적인 확장 없이 성능을 향상 시킬 수 있게 한다. 실험은 대상 플랫폼인 CT3400에서 수행하고 그 결과를 제시한다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집(한일합동학술편); 한국과학기술대학, 충남; 16-17 Oct. 1987
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• pp.863-869
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• 1987

INFOBUS, which has been designed as a system bus of a multiprocessor system, will be introduced. And the concepts of the multiple transfer and ORed write transfer will be described. These concepts make INFOBUS to be well suited for use as the system bus of the multiprocessor based programmable controller(MBPC). In addition, the mean data transfer time through INFOBUS, which is one of the most significant performance of a bus, will be obtained by analysis and simulation. Next, MBPC which uses INFOBUS as its system bus will be introduced, and some basic characteristics of MBPC will be described. The construction of exact model for MBPC will be given and simulated using SDL/SIM package. The reference system of our model will be briefly described also. Some results from the simulation will be given and validated.

• 한국시뮬레이션학회논문지
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• 제2권1호
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• pp.13-22
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• 1993

In a multiple-bus multiprocessor system in which processors and memory modulus are interconnected through system buses, time delay due to bus contention degrades system performance. In order to reduce such a problem , and optimal bus arbitration scheme and its hardware are neccessary. In this study, performaces of four arbitration schemes are analyzed and compared : fixed-priority, equal-priority, rotating-priority and round-robin priority schemes. For the study, the software simulator of a multiple-bus multiprocessor system is developed by using SLAM II. Simulation results show that, when memory sccesses are evenly distributed to all memory modulus, round-robin priority scheme provides the best performance. But when a hot spot exists, the use of the fixed priority scheme results in the shortest access time.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.751-754
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• 1998

This research aims at developing a single chip multiprocessor for high-performance computer system. Our design approach is to design a relatively small and simple processor unit and to integrate multiple copies of the unit in an efficient way. The proposed multiprocessor is composed of four CPUs and one graphic coprocessor. The four CPUs share the graphic coprocessor and each CPU implements the 64-bit SPARC-V9 instruction set architecture. This paper gives an overview of the proposed microarchitecture and discusses the considerations made in the course of the design.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.39-41
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• 2004

In this paper, I propose a thread scheduling policy for faster packet processing on the network processors with multithreaded multiprocessor architecture. To implement the proposed policy, I derived several basic parameters related to the thread scheduling and included a new parameter representing the packet contents and the features of the multithreaded architecture. Through the empirical study using a network processor, I proved the proposed scheduling ploicy provides better throughput and load balancing compared to the generally used thread scheduling policy.