• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.991-992
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• 2006

Multiprocessor system is efficient and high performance architecture to overcome a limitation of single core SoC. In this paper, we propose a multiprocessor SoC (MPSoC) architecture which provides the low complexity and the high performance. The dynamic routing scheme has a serious problem in which the complexity of routing increases exponentially. We solve this problem by making a cluster with several PEs (Processing Element). In inter-cluster network, we use deterministic routing scheme and in intra-cluster network, we use dynamic routing scheme. In order to control the hierarchical network, we propose efficient router architecture by using smart crossbar switch. We modeled 2-D mesh topology and used simulator based on C/C++. The results of this routing scheme show that our approach has less complexity and improved throughput as compared with the pure deterministic routing architecture and the pure dynamic routing architecture.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.2
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• pp.62-68
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• 1998

In this paper, we proposed the design of the intelligent traffic control system by using multiprocessor architecture. The inter-processor communication of the architecture is implemented by sharing the serial communication channel. In comparing the conventional traffic control system using single processor architecture, the proposed system uses multiple processors controlling the sub systems such as the signal lights, traffic measurement unit, auxiliary signal lights and peripherals. The main processor controls the communication among the processors and the communication protocol link to the central control center at remote site. The proposed architecture reduces the load and simplifies the program of each processor and enables the real time processing of the add-on features of intelligent traffic control systems. The architecture is implemented and the common channel inter-processor communications and the real time operation is experimented .experimented .

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.45-52
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• 1994

In recent days low cost, high performance microprocessors have led to construction of medium scale shared memory multiprocessor systems with shared bus. Such multiprocessor systems are heavily influenced by the structures of memory systems and memory systems become more important factor in design space as microprocessors are getting faster. Even though local cache memories are very common for such systems, the latency on access to the shared memory limits throughput and scalability. There have been many researches on the memory structure for multiprocessor systems. In this paper, an asynchronous memory architecture is proposed to utilize the bandwith of system bus effectively as well as to provide flexibility of implementation. The effect of the proposed architecture if shown by simulation. We choose, as our model of the shared bus is HiPi+Bus which is designed by ETRI to meet the requirements of the High-Speed Midrange Computer System. The simulation is done by using Verilog hardware decription language. With this simulation, it is explored that the proposed asynchronous memory architecture keeps the utilization of system bus low enough to provide better throughput and scalibility. The implementation trade-offs are also described in this paper. The asynchronous memory is implemented and tested under the prototype testing environment by using test program. This intensive test has validated the operation of the proposed architecture.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.249-258
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• 2002

One of the jai or purposes of multiprocessor system is to get a high efficiency in performance improvement. But in most cases, it is unavoidable to use some special programming languages or tools for full use of multiprocessor system. In general, loop and recursive call statements of algorithms are considered as typical parts for parallelization. Especially, recursive call statements are easy to parallelize conceptually without support of any special languages or tools. But it is difficult to control the degree of parallelism caused by high depth of recursive call leading to execution crash. This paper proposes a device to control Parallelism in the process of POSIX thread bated parallelization of recursive algorithms. For this, we define the concept of thread and process in UNIX system, and analyze the results of experimental application of the device to quick sorting algorithm.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.473-486
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• 2004

NUMA systems have remote access caches(RAC) in each local node to reduce the overhead for repeated remote memory accesses. By this RAC, memory latency and network traffic can be reduced and the performance of the multiprocessor system can be improved. Until now, several cache replacement policies have been proposed in recent years, and there also is cache replacement policy for multiprocessor systems. In this paper, we propose a cache replacement policy which is based on cache line coherence information. In this policy, the cache line that does not have an ownership is replaced first with respect to cache line that has an ownership. Like this way, the overhead to transfer ownership is avoided and the memory latency can be decreased. We also propose “Keeping-Ownership replacement policy with MRU (KOM)” and “Keeping-Ownership replacement policy with Reference Bit(KORB)” to reduce the frequent replacement penalty of the ownership-lacking cache line. We compare and analyze these with LRU and Pseudo LRU(PLRU). The simulation shows that KOM outperforms the PLRU by 25%, and KORB outperforms the PLRU by 13%. Although the hardware cost of KOM is very small, the performance of KOM is nearly equal to that of the LRU.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.107-109
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• 1998

효율적인 스케줄링 알고리즘은 적은 문맥교환 횟수를 가지면서 동시에 잘 정의된 임의의 태스크 집합에 대해 높은 스케줄링 성공률을 갖고 있어야 한다. 기존의 단일 프로세서 스케줄링 알고리즘들은 멀티프로세서 스케줄링 알고리즘들에 비해 시간 복잡도가 낮지만 멀티프로세서 환경에서 그대로 적용시킬 경우 스케줄링 성공률이 많이 떨어진다. 본 논문에서는 비슷한 시간 복잡도를 가지면서도 멀티프로세서 환경에서 높은 성공률을 얻을 수 있는 EDF-ZLP와 LLF-RP 알고리즘을 제안하고 이 알고리즘들의 추가적인 성능 향상 방안을 제안한다.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06a
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• pp.250-251
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• 2007

• Electronics and Telecommunications Trends
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• v.12 no.1 s.43
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• pp.15-25
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• 1997

적어도 20~30년 내에 완전한 ATM 망이 운용되기 위해서 음성 및 데이터와 같은 기존 협대역 통신뿐 아니라 대화형 TV같은 새로운 타입의 광대역 통신이 가능한 대용량 시스템이 요구되므로, 기존의 일반적인 ATM 교환기의 다중프로세서 시스템 구조 및 특성을 살펴보고, 초고속 정보 통신망 환경에 부합되는 대용량 ATM 시스템을 위한 새로운 다중프로세서의 구조를 고찰함으로써 미래의 시스템 설계 방향을 제시한다.

• Journal of the Korea Society for Simulation
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• v.4 no.2
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• pp.1-16
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• 1995

The performance of a computer system depends on the system architecture and workload, and the high performance required in many applications can be achieved by the scalability of the system architecture and workload. This paper presents scalable workload, a performance metric of scalable speedup and hierarchical modeling for the scalable computer system as well as the development of the object-oriented simulator spmplC++ Which is an advanced C++ version of the discrete event-driven simulation environment smplE. In addition, this paper presents two examples of applying scalable speedup, hierarchical modeling and simulator smplC++ to analyze the performance effect of the sclcbility in a multiprocessor system and a network-based client/server system.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.4 no.1
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• pp.11-15
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• 1986

In the new futre, computer system designers are expeted to bring more computer power to more people than is currently feasible. At the same time. it is reasonable for the computer system desigers to expect the computer architects to prodce hardware structures incorporating system algorithms of greated complexity so that more of the general instructions go to serving the users. In the past, the architect has delivered more computing to the user by constructing bigger and faster central processors, possibly connecting two or three CPUs together This approach has its limitations, in cost, complexity and reliability. In this paper, we first briefly discuss the hardware environment on which Hydra was implemented, then discuss the philosophy on which the system is based, and finally exhibit the protection mechanism.