• 한국정보통신학회논문지
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• 제10권4호
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• pp.645-651
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• 2006

본 논문은 컴퓨터 시스템의 성능평가와 분석을 대칭구조의 멀티프로세서를 실행할 수 있는 시뮬레이터를 사용하여 살펴보았으며 또한 시스템 분석을 하는데 있어서 멀티프로세서를 위한 멀티프로그램 벤치마크의 집합체인 SPLASH-2를 이행하여 대칭구조의 운영체제 IRIX5.3 탑재한 멀티프로세서의 행위범위의 연구를 수행하기 위하여 멀티프로세서의 시스템 분석을 실시 하였다. 또한 대칭구조의 멀티프로세서의 구조와 평가방법을 보다 유효하게 하기 위해서 멀티프로세서의 확장성을 functionality-based 소프트웨어인 SimOS를 가지고 증명하였으며 본 논문을 통하여 멀티프로그램 벤치마크인 RADIX 정렬 알고리즘이나 Cholesky 인수분해 알고리즘을 이용하여 로칼 인스트럭션과 로칼 데이터 사이에서의 멀티프로세서의 Cache miss의 수 와 Stall 시간을 동시에 검사하였다.

• 한국시뮬레이션학회논문지
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• 제8권1호
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• pp.35-49
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• 1999

The CC-NUMA based, distributed shared memory is an emerging architecture for multiprocessor computer systems because of its scalability and easy of programming. In this paper, we analyzed performance of a ring-based, CC-NUMA multiprocessor computer system using a commercial workload targeted for popular OLTP applications. Based on the traces collected from real machines, the characteristics of the commercial workload could be obtained. The simulation results showed that the bottleneck on the ring could be effectively removed by using a dual ring structure. We believe our simulation methodology and results will help us to design better multiprocessor computer systems for commercial application domains.

• 전기학회논문지
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• 제57권3호
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• pp.421-428
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• 2008

The DVS(Dynamic Voltage Scaling) technique is the method to reduce the dynamic energy consumption. As using slack times, it extends the execution time of the big load operations by changing the frequency and the voltage of variable voltage processors. Researches, that controlling the energy consumption of the processors and the data transmission among processors by controlling the bandwidth to reduce the energy consumption of the entire system, have been going on. Since operations in multiprocessor systems have the data dependency between processors, however, the DVS techniques devised for single processors are not suitable to improve the energy efficiency of multiprocessor systems. We propose the new scheduling algorithm based on DVS for increasing energy efficiency of multiprocessor systems. The proposed DVS algorithm can improve the energy efficiency of the entire system because it controls frequency and voltages having the data dependency among processors.

• 전기전자학회논문지
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• 제8권2호
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• pp.207-215
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• 2004

계층버스 다중처리기 시스템에서 캐시 일관성 프로토콜은 시스템 성능에 영향을 준다. 특정 캐시 일관성 프로토콜 하에서 시스템의 성능은 버스의 대역폭 및 메모리크기, 메모리 블록의 크기에 따라 영향을 받는다. 따라서 시스템 성능에 영향을 미치는 요소들에 대한 민감도 분석이 필요하다. 본 논문에서는 계층버스 다중처리기에 캐시 일관성 프로토콜을 적용하고, 프로토콜에서 정의된 상태가 나타날 확률을 구하였다. 구해진 확률값을 분석적 모델에 적용하여 시뮬레이션을 하였다. 그리고 시뮬레이션 결과를 기반으로 시스템의 성능에 영향을 미치는 요소에 대한 민감도 분석을 하였다.

• 한국멀티미디어학회논문지
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• 제8권12호
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• pp.1605-1612
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• 2005

This paper presents the knowledge and experience we obtained by employing multiprocessor systems as a computer simulation design verification to study high-performance computing system. This paper also describes a case study of symmetric multiprocessors (SMP) kernel on a 32 CPUs CC-NUMA architecture using an actual architecture. A small group of CPUs of CC-NUMA, high-performance computer system, is clustered into a processing node or cluster. By simulating the system design verification tools; we discussed SMP OS kernel on a CC-NUMA multiprocessor architecture performance which is $32\%$ of the total execution time and remote memory access latency is occupied $43\%$ of the OS time. In this paper, we demonstrated our simulation results for multiprocessor, high-performance computing system performance, using simulation-based design verification.

• Journal of Computing Science and Engineering
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• 제7권1호
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• pp.30-43
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• 2013

Multicore and multiprocessor systems with dynamic voltage scaling architectures are being used as one of the solutions to satisfy the growing needs of high performance applications with low power constraints. An important aspect that has propelled this solution is effective task/application scheduling and mapping algorithms for multiprocessor systems. This work proposes an energy aware, offline, probability-based unified scheduling and mapping algorithm for multiprocessor systems, to minimize the number of processors used, maximize the utilization of the processors, and optimize the energy consumption of the multiprocessor system. The proposed algorithm is implemented, simulated and evaluated with synthetic task graphs, and compared with classical scheduling algorithms for the number of processors required, utilization of processors, and energy consumed by the processors for execution of the application task graphs.

• 한국멀티미디어학회논문지
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• 제9권1호
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• pp.119-126
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• 2006

멀티 프로세서 시스템에서 스케쥴링은 매우 중요한 부분이지만, 최적의 해를 구하는 것이 복잡하여 최근 다양한 휴리스틱 방법들에 의한 스케쥴링 알고리즘들이 제안되고 있다. 본 논문에서는 유전 알고리즘을 이용한 새로운 스케쥴링 알고리즘을 제시한다. 또한, 해를 구하는 과정에서 시뮬레이티드 어닐링 (simulated annealing)의 확률을 이용하여 유전 알고리즘의 성능을 개선시킨다. 제시된 알고리즘은 태스크들의 최종 수행 완료 시간 (makespan)을 최소화하는 것을 목표로 한다. 모의 실험을 통하여 제시된 알고리즘이 다른 알고리즘보다 최종 수행 완료 시간이 작음을 확인할 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.408-411
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• 1999

Microarchitecture simulator is an important tool to verify and optimize the microarchitecture of a new microprocessor. Moreover. it can be use as a performance simulator to estimate the target microprocessor′s performance. And system software designers can use it as a software developing environment. This paper describes a "microarchitecture simulator for on-chip Multiprocessor microprocessor". It is a program-driven and cycle-based simulator that can execute simultaneous mutithreading benchmarks. We verified the microarchitecture of a new on-chip multiprocessor microprocessor with it and did performance simulations to estimate the performance of the on-chip multiprocessor microprocessor.

• 전자통신동향분석
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• 제13권5호통권53호
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• pp.11-22
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• 1998

Recently, scalable multiprocessor systems are actively developed for general-purpose computing, which are based on distributed shared memory (DSM) architecture to boost up both programmability and scalability. In this paper, we survey and analyze cache coherence protocols in non-uniform memory access (NUMA) multiprocessor systems. In particular, it has been easily inferred that specialized hardware suitable for NUMA multiprocessor systems with commodity symmetric multiprocessors (SMPs) is highly required. The cache coherence protocol combined with specialized hardware can significantly improve the performance and scalability of NUMA multiprocessor systems, providing better programmability.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.140.3-140
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• 2001

This paper analyzes a blocking that is due to shared resource in multiprocessor system. A proposed analysis for shared resource suggests a scalable and amendable scheduling method about task allocation. An equation of shared resource blocking is proposed by a throughput at common bus and a ratio of throughput during time period, it is included a parameter of tasks scheduling. Using this equation, a new guideline for task allocation of multiprocessor is presented. Finally, in proposed system a model simulations for the proposed blocking model is given by a deterministic ratio of shared resource.