• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.251-257
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• 2016

The multi-core technology has become pervasive in embedded systems. An implementation of the Doppler Beam Sharpening algorithm that improves the azimuth resolution by using doppler frequency shift is possible only in multi-core environment because of the amount of calculation. In this paper, we design of multi-core architecture for a real time implementation of DBS algorithm. And based on designed structure, we produce a DBS image on P4080 board.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.762-767
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• 1999

객체 인식은 고성능 컴퓨팅을 필요로 하는 흥미있는 응용 분야이다. 현재 대부분의 고성능 컴퓨터는 슈퍼스칼라 구조의 범용 마이크로프로세서를 채택하고 있으나, 반도체 집적도가 증가함에 따라 슈퍼스칼라 구조를 대신할 새로운 마이크로프로세서가 구조가 제안되고 있다. 본 논문에서는 최근 새로운 마이크로프로세서 구조로 급부상하고 있는 다중처리 마이크로프로세서 구조가 객체 인식 응용에 적합한지를 분석한다. 성능 특성을 확인하기 위하여 먼저 프로그램 구동방식의 마이크로프로세서 시뮬레이터와 프로그래밍 환경을 개발하였다. 이를 기반으로 시뮬레이션을 수행한 결과, 다중처리 마이크로프로세서가 작은 오버헤드로 쓰레드 수준의 병렬성을 적절히 활용하고 있어 객체 인식 응용에 적합한 구조임을 확인하였다.

• Journal of Communications and Networks
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• v.16 no.4
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• pp.436-446
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• 2014

The high intensity of research and modeling in fields of mathematics, physics, biology and chemistry requires new computing resources. For the big computational complexity of such tasks computing time is large and costly. The most efficient way to increase efficiency is to adopt parallel principles. Purpose of this paper is to present the issue of parallel computing with emphasis on the analysis of parallel systems, the impact of communication delays on their efficiency and on overall execution time. Paper focuses is on finite algorithms for solving systems of linear equations, namely the matrix manipulation (Gauss elimination method, GEM). Algorithms are designed for architectures with shared memory (open multiprocessing, openMP), distributed-memory (message passing interface, MPI) and for their combination (MPI + openMP). The properties of the algorithms were analytically determined and they were experimentally verified. The conclusions are drawn for theory and practice.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.777-785
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• 1987

In this paper, a tightly-coupled multiprocessor system is implemented with four processing elements based on MC68000 CPU, a common menory (128KB), and a single time-shared bus. The multi-tasking operating system, MTOS, is modified so that the multiprocessor system can support multitasking and multiprocessing. The performance of the proposed system is evaluated by stochastic Petri Net system modeling. The efficiency and the processing power are simulated for various load factors and up to 16 PEs. By running benchmark programs, such as quicksort, FFT, and matrix-multiplication, the speed of parallel processing is compared with that of a single processor.

• The Journal of the Acoustical Society of Korea
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• v.12 no.4
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• pp.32-38
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• 1993

2-D FIR 필터를 시스토릭 어레이 구조로 실현하는 방법을 제시하였다. 시스토릭 어레이는 1-D FIR 필터로 부분 실현한 후 병렬연겨랗여 구현하였다. 부분 실현한 시스토릭 어레이의 마지막 입력신호를 다음 단의 입력에 직접연결시킴으로써 입력 지연에 사용되는저장요소를 절약 시킨다. 1-D 시스ㅏ토릭 어레이는 지역통신 접근에 의해 DG를 설계한 후 SFG로으ㅟ 사상을 통해 유도하였다. 유도된 SFG는 DG의 노드가 보다 적은수의 PE에 사상됨으로써 PE의 이용률을 개선할 수 잇다. 유도된 구조는 매우 간단하며, 입력 샘플이 공급되어지면 매 샘플링 기간마다 새로운 출력을 얻는 매우 SHB은 데이터 비율(data rate)을 갖는다. 시스토릭 어레이는 규칙적이고, 모듈성이며, local interconnection, highly synchronized multiprocessing 의 특징을 갖기 때문에 VLSI 실현에 매우 적합하다. PE 셀 구조는 높은 처리율, 최소 계산시간과 최소 파이프라인 주기를 갖도록 설계하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.781-784
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• 2005

현재 모바일 시스템에서는 무선 인터넷이 보급됨에 따라 개인 휴대용 단말 장치(PDA)와 같은 모바일 PC를 이용하여 실시간으로 Server에 접속할 수 있다. 예를 들면 모바일을 이용한 진료 시스템에서는 원격으로 임상 정보 및 환자 정보 등을 볼 수 있다. 모바일 PC로 이러한 정보를 볼 수 있다는 것은 일반 PC로 진료 시스템에 접속하여 사용했었던 기존의 방식보다 편리성, 이동성 면에서 매우 좋은 평가를 받고 있다. 그러나 휴대성을 목적으로 만들어진 모바일 PC는 작은 Display 장치로 인하여 진료에 한계가 있고 원격 통신을 하기에는 많은 Client의 요구를 한 Server에서 처리하기는 매우 힘들다. 따라서 본 논문은 이런 문제점을 개선하기 위하여 X-ray나 MRI 등의 진료 이미지를 다양한 Server에서 처리하여 단말 장치에 전송하고 효율적인 다중처리시스템을 제안한다.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1212-1218
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• 1999

This paper proposes a new multipath interconnection network(MIN) structure for improving performance which uses widely in the design of multiprocessing, ATM system and VOD server. For improving performance such as passthrough ratio and packet latency, it proposes new routing method which routes one of the collided packets into the i+1-th switching stage of the adding Banyan MIN network when it occurred collision at the i-th switching stage of the basic MIN again when they collide each other. The new improved performance MIN network has been compared with MBSF, TBSF and PBSF structured MIN network from the viewpoint of passthrough ratio and the number of switching stage vs. passthrough ratio. It is shown to improve a performance and to be a simple structure which reducing the number of switching stage of adding MIN in comparison with other structured MIN including TBSF.

• Nuclear Engineering and Technology
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• v.55 no.3
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• pp.1015-1020
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• 2023

A multi-layer design is applied to mitigate single event effect (SEE) in a 28 nm System-on-Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system watchdog. Irradiation tests utilized 70 and 90 MeV proton beams to examine its performance through comparative analysis. Via examining SEEs in on-chip memory (OCM), compared with the trial without applying the multi-layer design, the test results demonstrate that the adopted multi-layer design can effectively mitigate SEEs in the SoC.

• The Transactions of the Korea Information Processing Society
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• v.7 no.7
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• pp.2219-2228
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• 2000

Caches in a multiprocessing environment introduce the cache coherence problem. When multiple processors maintain locally cached copies of a unique shared-memory location, any local modification of the location can result in a globally inconsistent view of memory. Cache coherence protocols are important to operate a shared-memory multiprocessor system with efficiency and correctness. Since random testing and simulations are not enough to validate correctness of protocols, it is necessary to develop efficient and reliable verification methods. In this appear we present our experience in using VIS (Verification Interacting with Synthesis), a tool of formal method, to analyze a number of property of a cache coherence protocol, RACE (Remote Access Cache coherent Enforcement).

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.5
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• pp.683-692
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• 1995

Many kinds of large scale multiprocessing and parallel-processing systems have recently been developed. The contention on the shared data caused by multiple processors may degrade system performance. So, processor synchronization has become one of the important issues in these systems. To solve the synchornization issues, a lot of software and hardware schemes based on spin lock have been proposed. Although software schemes are easy to implement, hardware schemes are preferred in many systems to gain optimized performance. This paper proposes an efficient processor synchronization scheme, called QCX,and describes its design considerations, hardware, algorithm, protocol. Also, in this paper, the performance of QCX has been evaluated with QOLB[5] and LBP[7] using a simulation. The simulation, with varying the number of processor and the contention on shared variables, measured the average execution times of a workload. The simulation results show that the performances of QCX is best when practicability is considered. QCX is more efficient than QOLB and LBP in two aspects. First, the hardware of QCX is more simple and cost-effective because the cache structure need not be changed. Secondly, QCX is more general because it uses a generic atomic instruction.