• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.7-14
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• 2009

Lately, NAND flash cards have been used to store massive amounts of multimedia data. However, these nand flash cells itself has a slow operation time and by that, the nand flash cards are not appropriate for high performance massive data transfer. Indeed, most flash card products have a disadvantage in that they require plenty of time to transfer massive amounts of data. Therefore, we propose a new architectural design for the hardware and software of the NAND flash cards by improving their data transfer rate. Our design is based on a multiprocessing which is different from the conventional serial processing method. We simulated our design under the VIP (Virtual IP) environment, and verified our work using FPGA test platforms. As a result, the downloading performances was approximately 160MB/s on VIP and 85.3MB/s on FPGA.

• Journal of KIISE
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• v.42 no.11
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• pp.1322-1331
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• 2015

According to the hypervisor scheduler, the vCPU (virtual CPU) operates under two states: the running state and the stop state. When the vCPU is in the stop state, incoming events are delayed until that vCPU's state changes to the running state. The latency in handling such events that are sent to the vCPU is regarded as the I/O latency. Since a SMP (symmetric multiprocessing) VM (virtual machine) incorporates multiple vCPUs, the event latency on a SMP VM can vary according to specific vCPU that receives the event. In this paper, we propose a new scheme named event routing that sends events according to the operation state of each vCPU to reduce the event latency on an SMP VM. We implemented the proposed event routing scheme in Xen ARM hypervisor and confirmed the reduction of I/O latency from measuring the network RTT (round trip time) and the TCP bandwidth under a variety of testing conditions. The network RTT decreases by up to 94% and the TCP bandwidth increases up to 35% when compare to native Xen ARM.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.6
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• pp.703-709
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• 2014

In the AMP(Asymmetric Multiprocessing) based dual core using core-specific operating system in a single processor system, shared memory method is used to send data between processors in dual core. To used shared memory in different operating systems, there is a problem of needing to solving the issue of message communication and synchronization between the two operations systems. In this paper, separate memory controller was used for data sharing between different processor cores in dual core environment. This controller can designate two slave ports to allow simultaneous access from two processors, and in the case of process data simultaneously by two processors, priority order of slave ports is determined through memory mediator. When sending data from A to B processor, SRAM area was logically separated into 8 pages. It allowed using memory area from multiple processes with the size of 4KByte per page, and control register with the size of 4Byte was used to discern the usability of current page.

• Database Research
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• v.34 no.3
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• pp.14-27
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• 2018

Recently, to alleviate the memory bottleneck problme occurred in Symmetric Multiprocessing (SMP) architecture, Non-Uniform Memory Access (NUMA) architecture was proposed. In addition, since an aggregation operator is an important operator providing properties and summary of data, the efficiency of the aggregation operator is crucial to overall performance of a system. Thus, in this paper, we propose an efficient aggregation processing technique on NUMA architecture. Our proposed technique consists of partition phase and merge phase. In the partition phase, the target relation is partitioned into several partial relations according to grouping attribute. Thus, since each thread can process aggregation operator on partial relation independently, we prevent the remote memory access during the merge phase. Furthermore, at the merge phase, we improve the performance of the aggregation processing by letting each thread compute aggregation with a local hash table as well as avoiding lock contention to merge aggregation results generated by all threads into one.

• Proceedings of the IEEK Conference
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• 2001.06c
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• pp.181-184
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• 2001

In recent, a morphological analyzer be used for indexing system in information retrieval system. A morphological analyzer as a indexing system must have multiprocessing ability to deal with multiple users and documents. To meet the needs of these, we propose a morphological analyzer with multi-threads method. To use multi-threads method, we consider memory allocation problem, threads synchronization problem, code optimization and so on. In this paper, first, we report several manners for multi-threads. And next, to evaluate our proposed system, we make a comparison test between proposed system and existing system.

• International Journal of Internet, Broadcasting and Communication
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• v.12 no.3
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• pp.87-94
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• 2020

Recently, computer hardware is evolving toward increasing the number of computing cores, not increasing the clock speed. In order to use the performance of parallelized hardware to the maximum, the running program must also be parallelized. However, software developers are accustomed to sequential programs, and in most cases, write programs that operate sequentially. They also have a lot of difficulty designing and developing software in parallel. We propose a method to automatically convert a sequential C/C++ program into a parallelized program, and develop a parallelization tool that supports it. It supports open multiprocessing (OpenMP) and parallel patterns library (PPL) as a parallel framework. Perfect automatic parallelization is difficult due to dynamic features such as pointer operation and polymorphism in C/C++ language. This study focuses on verifying the conditions of parallelization rather than focusing on fully automatic parallelization, and providing advice to developers in detail if parallelization is not possible.

• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.68-75
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• 1999

In this paper, we propose a Baysian method estimating system reliability which is more effective and precise than conventional methods using prior information. This technique estimates system reliabilities that an entire system and multiprocessing system is normally working in multiprocessor system and multiple port connected memory architecture. The reason is why internetwork with multiprocessor system is mainly connected as multiple bus structure, crossbar switching structure and multiport connected memory structure.

• Proceedings of the Acoustical Society of Korea Conference
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• 1992.06a
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• pp.29-32
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• 1992

In this paper, a systolic array structure is derived from the realization of 2-D IIR digital filters directed from the SFG(signal flow graph). After realized the 1-D formed partial systolic array, we implemented the complete systolic array to be cascaded 1-D form. The cascading of partial systolic arrays reduce the storage element which sued to delay input signal. 1-D systolic array is derived from that DG is designed through local communication approach and then it mapping to SFG. The derived structure is very simple and has high throughput because during new imput sample is supplied, new output is obtained every sampling period. And broadcast input signal is eliminated. Since the systolic array has property of regularity, modularity, local interconnection and highly synchronized multiprocessing, thus is very suitable for VLSI implementation.

• Journal of Biomedical Engineering Research
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• v.14 no.4
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• pp.315-320
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• 1993

This paper deals with a subject for implementation of L+ayer 1 and Layer 2(LAPD) of ISDN user-network interface on the basis of CCITT recommandation I.411, I.412, I.441 (Q.921), I.450(Q.930) and I.451 (Q.931) for ultrasonic image transfer. For the implementa tion of LAPD protocol of ISDN in this study. PC-CARD based hardware(TA :Terminal Adopt) is proposed and operating system (PC-XINU) supporting the Multiprocessing is transplanted to it. As the Service Access Point(SAP) is accessed by using the port of XINU and Layers which consist of transmitting and receiving part are independantly processed for each other in this proposed system. It can be easy and flexible to implement LAPD protocol for the message transfer.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06d
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• pp.16-18
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• 2012

이 논문은 멀티프로세싱으로 인해서 발생할 수 있는 touch screen polling I/O 성능 이슈를 다루고 있다. Touch screen이 장착된 휴대용기기가 점차 대중화되고 그 편한 사용성 만큼이나 쉽게 익숙해지고 있다. 하지만, 휴대용기기내에서 여러 가지 작업(multiprocessing or multitasking)을 동시에 처리하면서 생기는 문제들 중에 touch screen의 반응이 의도하지 않은 동작결과로 나타나는 경험을 하게 된다. 이 논문에서 이러한 부분에 집중하여 우선순위가 높은 다른 작업(process or task)과 동시에 touch screen 처리과정을 분석하여 개선책을 제안코자 한다. 또한 우리는 이러한 개선책을 증명하기 위해서 실제 구현을 통해서 확인한다. 개선된 방법은 이 상황과 비슷한 조건에서 활용이 가능할 것으로 판단한다.