• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.6
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• pp.568-572
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• 2009

We present a ternary microfluidic multiplexer unit, capable to address three flow channels using a pair of control lines with two different threshold pressure valves. The previous binary multiplexer unit addresses only two flow channels using a pair of control line with identical threshold pressure valves, thus addressing $2^{n/2}$ flow channels using n control lines. The present ternary multiplexer addressing three flow channels using a pair of control lines, however, is capable to address $3^{n/2}$ flow channels using n control lines with two different threshold pressure valves. In the experimental study, we characterized the threshold pressure and the response time of the valves used in the ternary multiplexer. From the experimental observation, we also verified that the present ternary multiplexer unit could be operated by two equivalent valve operating conditions: the different static pressures and dynamic pressures at different duty ratio. And then, $3{\times}3$ well array stacking ternary multiplexers in serial is addressed in cross and plus patterns, thus demonstrating the individual flow channel addressing capability of the ternary multiplexer. Thus, the present ternary multiplexer reduces the number of control lines for addressing flow channels, achieving the high well control efficiency required for simple and compact microfluidic systems.

• Journal of applied mathematics & informatics
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• v.8 no.1
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• pp.81-95
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• 2001

This paper models and evaluates the AAL multiplexer to analyze AAL protocol in ATM networks. We consider an AAL multiplexer in which a single periodically determinsitic CBR traffic stream and several variable size bursty background traffic streams are multiplexed and one ATM cell stream goes out. We model the AAL multiplexer as a B/sup X/ + D/D/1/K queue and analyze this queueing system. We represent various performance measures such as loss probability and waiting time in the basis of cell and packet.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.6
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• pp.787-798
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• 1995

We implement the E-plane T-juncition manifold mutiplexer having low insertion loss for output multiplexer of Ku-band satellite transponder. Manifold multiplexer implemented here is composed of 2 channel filters, T-junctions, half-wave waveguide connecting channel filters and manifold, and manifold itself.[1-4] Considering the mass and volume of the satellite transponder, the channel filters are designed to dual-mode.[5-13] And Elliptic filter function is used, which has good characteristics of suppressing the interference between 2 channels. Since the performance of manifold multiplexer depends on the manifold waveguide transmission line length, it's necessary proper analysis. In this paper, we do optimization process of T-junction and other elements by using CAD and implement the manifold multiplexer. An experiment shows that characteristic response of multiplexer matches wel its modeling result.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.2
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• pp.147-154
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• 1990

A 4:1 Time Division Multiplexer(MUX) had been designed in using GaAs Source Coupled FET Logic(SCFL), Designed Multiplexer uses a time division frequency divider and two stage of singnal combining 2:1 multiplexer. The performance of the multiplexer is verified by PSPICE simulation. Designed circuit operates up to 12.5Gbit/s with a power dissipation of 192mW. These performance are more advanced than other reported multiplexer in the speed and power dissipation.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.2
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• pp.93-99
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• 2011

In this paper, an ATSC(Advanced Television Standard Committee)-M/H(Mobile/Handheld) multiplexer is designed and implemented using an embedded Linux based hardware platform. The ATSC-M/H multiplexer is composed of a CPU(Central Processor Unit), an FPGA(Field-Programmable Gate Array), ASI(Asynchronous Serial Interface)/SMPTE310(Society of Motion Picture and Television Engineers310) interface board, and a GPS(Global Position System) clock processing block. The main functions of the ATSC-M/H multiplexer executed in the CPU and FPGA are described. The operation of the ATSC-M/H multiplexer is verified by processing its broadcast signal on a commercial receiver analyzer.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.682-685
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• 2002

In this paper, we defined necessary operations and functional blocks of a multiplexer for 3-D video systems and present our multiplexer design. We adopted the ITU-T's recommendation(H.222.0) to define the operations and functions of the multiplexer and explained the data structures and details of the design for multiview image processing. The data structure of TS(Transport Stream) and PES (Packetized Elementary Stream) in ITU-T Recommendation H.222.0 does not fit our multiview image processing system, because this recommendation is fur wide scope of transmission of non-telephone signals. Therefore, we modified these TS and PES stream structures. The TS is modified to DSS(3D System Stream) and PES is modified to SPDU(DSS Program Data Unit). We constructed the multiplexer through these modified DSS and SPDU. The number of multiview image channels is nine, and the image class employed is MPEG-2 SD(Standard Definition) level which requires a bandwidth of 2∼6 Mbps. The required clock speed should be faster than 54(= 6 ${\times}$ 9)㎒ which is the outer interface clock speed. The inside part of the multiplexer requires a clock speed of only 1/8 of 54㎒, since the inside part of the multiplexer operates by the unit of byte. we used ALTERA Quartus II and the FPGA verification for the simulation.

• Journal of Digital Contents Society
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• v.18 no.5
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• pp.881-888
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• 2017

Logic design using multiplexer has been used as a useful method for design convenience and flexibility in structural digital system design. In this paper, we analyze the effect of don't care conditions on logic optimization in a multiplexer-based logic design, which was not discussed enough in the previous studies in multiplexer based logic design, and describe the use of don't care conditions for designing of a single multiplexer and multiple multiplexer-based logic design. Especially, the design method when the number of data input is not 2m (as the number of selection lines is m) is considered. We also describe how to apply the proposed technique to the digital logic design education in conjunction with microprocessor design using Arduino which is widely used in creative engineering education recently.

• Journal of Information Display
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• v.9 no.3
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• pp.1-7
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• 2008

With the aim of creating a high-quality display system with value-added functions, we designed a current mode multiplexer for LTPS TFT devices. The multiplexers had less than 1 volt logic swing, and speed improvement was evident compared with that of conventional CMOS architecture. We refined the multiplexer to achieve a more stable current steering operation. By using the versatility of the multiplexer, a new NAND/AND and NOR/OR logic gates were designed through the simple modification of signal connections. Two micron LTPS TFT parameters were used during the HSPICE simulation of the circuits.

• IE interfaces
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• v.18 no.4
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• pp.494-503
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• 2005

This paper considers the problem of performance analysis for the multiplexer, when homogeneous periodic on-off sources are statistically multiplexed. Periodic on-off source model is defined that on-period and off-period are repeated by once in a deterministic periodic time and in on-period, cell arrives with deterministic time interval. In order to reflect periodicity of source model, we consider two multiplexing situation, such as random multiplexing and synchronized multiplexing. In both case, we obtain the overload-period distribution in the multiplexer, and an approximate method using the overload period distribution is suggested for obtaining the CLP(Cell Loss Probability) in the buffer of the multiplexer. A numerical example using MPEG-I real traffic samples and the results are also presented.

• International Journal of Advanced Culture Technology
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• v.10 no.3
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• pp.332-338
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• 2022

The article presents a concept of designing a Multiplexer circuit which acts as a "Selector" and that becomes capable to select different speed created at different TTL Gate configurations; Standard TTL(Normal Speed), High Speed TTL(High Speed), Schottky TTL(Super High Speed) and further connect the selected Gate speed to the CAR shape created using C-Programming at Computer Graphics and finally CAR shape display at different speed to the color TV. The Multiplexer supporting efficient and more reliable selection criteria using "Logical based selection criteria" and further the output from multiplexer is provided to CAR shape created using c-programming and finally CAR shape is display to color TV system. Basic purposes and assumptions regarding the design and development of this system as well as a description of its operation have been presented.