• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.4
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• pp.311-314
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• 2001

Recently, research on Intelligent Information Process has actively been under way JD various areas and gradually extended to be adaptive to uncertain and complex dynamic environments. This paper presents a Multiple Valued Logic Automata(MVL-Automata) Model, utilizing properties of difference in a Multiple Valued Logic function. That is, MVL-Automata is able to be autonomously adapted to dynamic changing since an input stling is mapped to the value of a Multiple Valued Logic function and the property of difference in a Multiple Valued Logic function is applied to state transition. Therefore, Multiple Valued Logic Automata can be widely applied to the modeling dynamically of changing environments.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.2 no.3
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• pp.215-220
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• 2002

This paper proposes a method to apply the Backpropagation(BP) algorithm of MVL(Multi-Valued Logic) Neural Network to pattern recognition. It extracts the property of an object density about an original pattern necessary for pattern processing and makes the property of the object density mapped to MVL. In addition, because it team the pattern by using multiple valued logic, it can reduce time f3r pattern and space fer memory to a minimum. There is, however, a demerit that existed MVL cannot adapt the change of circumstance. Through changing input into MVL function, not direct input of an existed Multiple pattern, and making it each variable loam by neural network after calculating each variable into liter function. Error has been reduced and convergence speed has become fast.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2002.12a
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• pp.502-505
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• 2002

본 논문은 다치(MVL:Multiple Valued Logic) 신경망의 BP(Backpropagation) 학습 알고리즘을 이용하여 패턴 인식에 이용하는 방법을 제안한다. MVL 신경망을 이용하여 패턴 인식에 이용함으로서, 네트워크에 필요한 시간 및 기억 공간을 최소화할 수 있고 환경 변화에 적응할 수 있는 가능성을 제시하였다. MVL 신경망은 다치 논리 함수를 기반으로 신경망을 구성하였으며, 입력은 리터럴 함수로 변환시키고, 출력은 MIN과 MAX 연산을 사용하여 구하였고, 학습을 하기 위해 다치 논리식의 편 미분을 사용하였다.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.32-40
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• 1999

The analysis of logic function is performed by the spectral coefficients which transform the function domain data into the spectral domain data. By using the spectral techniques, analysis of MVL circuits is performaed, and the fault analysis and detecting methods of multiple-valued logic circuits are proposed in this paper.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.55-61
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• 1994

The multiple valued logic(MVL) circuit with ROM type using current mode CMOS is presented in this paper. This circuit is composed of the multiple valued-to-binary(MV/B) decoder and the selection circuit. The MV/B decoder decodes the single input multiple valued signal to N binary signal, and the selection circuits is composed N$\times$N array of the selecion cells with ROM types. The selection cell is realized with the current mirror circuits and the inhibit circuits. The presented circuit is suitable for designing the circuit of MVL functions with independent variables, and reduces the number of selection cells for designing the circuit of symmetric MVL functions as many as {($N^2$-N)/2}+N. This circuit possess features of simplicity. expansibility for array and regularity, modularity for the wire routing. Also, it is suitable for VLSI implementation.

• Journal of the Korean Institute of Intelligent Systems
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• v.19 no.1
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• pp.13-18
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• 2009

Usually, human emotions are vague and change diversely on the basis of the stimulus from the outside. Plutchik classified the fundamental behavioral patterns into eight patterns, named each of them a genuine emotion, and furthermore suggested mixed emotions using a combination of genuine emotions. In this paper, we propose a method for processing Plutchik's emotion model using Multiple Valued Logic(MVL) Automata Model which utilizes the properties of difference in Multiple Valued Logic functions. This proposed emotion processing model can be widely applied to the analysis and processing of emotion data.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.3
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• pp.134-142
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• 2005

The implementation of Multiple-Valued Logic(MVL) based on Current-Mode CMOS Logic(CMCL) circuits has recently been achieved. In this paper, four-valued Unary Multiple-Valued logic functions are synthesized using current-mode CMOS logic circuits. We properly make use of the fact that the CMCL addition of logic values represented using discrete current values can be performed at no cost and that negative logic values are readily available via reversing the direction of current flow. A synthesis process for CMCL circuits is based upon a logically complete set of basic elements. Proposed algorithm results in less expensive realization than those achieved using existing techniques in terms of the number of transistors needed. As an alternative to the cost-table techniques Universal Unary Programmable Circuit (UUPC) for a unary function is also proposed.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.11
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• pp.56-64
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• 1992

The sum-of-product type MVL (Multiple-valued logic) functions can be directly transformed into the exclusive-sum-of-literal-product(ESOLP) type MVL functions with a substitution of the OR operator with the exclusive-OR(XOR) operator. This paper presents an algorithm that can reduce the number of minterms for the purpose of minimizing the hardware size and the complexity of the circuit in the realization of ESOLP-type MVL functions. In Boolean algebra, the joinable true minterms can form the cube, and if some cubes form a cube-chain with adjacent cubes by the insertion of false cubes(or, false minterms), then the created cube-chain can become a large cube which includes previous cubes. As a result of the cube grouping, the number of minterms can be reduced artificially. Since ESOLP-type MVL functions take the MIN/XOR structure, a XOR circuit and a four-valued MIN/XOR dynamic-CMOS PLA circuit is designed for the realization of the minimized functions, and PSPICE simulation results have been also presented for the validation of the proposed algorithm.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.57-63
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• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.135-143
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• 2003

This paper describes the design techniques of the data converters for Multiple-Valued Logic(MVL). A 3.3V low power 4 digit CMOS analog to quaternary converter (AQC) and quaternary to analog converter (QAC) mainly designed with the neuron MOS down literal circuit block has been introduced. The neuron MOS down literal architecture allows the designed AQC and QAC to accept analog and 4 level voltage inputs, and enables the proposed circuits to have the multi-threshold properity. Low power consumption of the AQC and QAC are achieved by utilizing the proposed architecture.