• Proceedings of the IEEK Conference
• /
• summer
• /
• pp.204-208
• /
• 2004

Embedded business will be expanded market more and more since customers seek more wearable and ubiquitous systems. Cellular telephones, PDAs, notebooks and portable multimedia devices could bring higher microprocessor revenues and more rewarding improvements in performance and functions. Increasing battery capacity is still creeping along the roadmap. Until a small practical fuel cell becomes available, microprocessor developers must come up with power-reduction methods. According to MPR 2003, the instruction and data caches of ARM920T processor consume $44\%$ of total processor power. The rest of it is split into the power consumptions of the integer core, memory management units, bus interface unit and other essential CPU circuitry. And the relationships among CPU, peripherals and caches may change in the future. The processor working on higher operating frequency will exact larger cache RAM and consume more energy. In this paper, we propose advanced low power trace cache which caches traces of the dynamic instruction stream, and reduces cache access times. And we evaluate the performance of the trace cache and estimate the power of the trace cache, which is compared with conventional cache.

• Annual Conference of KIPS
• /
• 2011.04a
• /
• pp.46-49
• /
• 2011

This paper is to implement MoIP platform to send and receive video and audio at the same time by using high-performance Dual Core Processor. Even if Wall-Pad key component of a home network system is released by using embedded processors, it's lacking of performance in terms of multimedia processing and feature of video telephony through which video and voice are exchanged simultaneously. The main reason could be that embedded processors currently being used do not provide enough performance to support both MoIP call features and various home network features simultaneously. In order to solve these problems, Dual processor could be used, but in the other hands it brings another disadvantage of high cost. Therefore, this study is to solve the home automation features and video telephony features by using Dual Core Processor based on ARM 11 Processor and implement the MoIP Wall-Pad which can reduce the board design costs and component costs, and improve performance. The platform designed and implemented in this paper verified performance of MoIP to exchange the video and voice at the same time under the situation of Ethernet network.

• Journal of Advanced Engineering and Technology
• /
• v.5 no.4
• /
• pp.349-353
• /
• 2012

Recently, Mobile multimedia equipments as smart phone and tablet pc requirement is increasing and this market is also being expanded. These mobile equipments require large multi-media function, so more power consumption is required. For these reasons, the needs of power management IC as switching type dc-dc converter and linear regulator have increased. DC-DC buck converter become more important in power management IC because the operating voltage of VLSI system is very low comparing to lithium-ion battery voltage. There are many people to be concerned about digital DC-DC converter without using external passive device recently. Digital controlled DC-DC converter is essential in mobile application to various external circumstance. This paper proposes the DC-DC Buck Converter using the AVR RISC 8-bit micro-processor control. The designed converter receives the input DC 18-30 [V] and the output voltage of DC-DC Converter changes by the feedback circuit using the A/D conversion function. Duty ratio is adjusted to maintain a constant output voltage 12 [V]. Proposed converter using the micro-processor control was compared to a typical boost converter. As a result, the current loss in the proposed converter was reduced about 10.7%. Input voltage and output voltage can be displayed on the LCD display to see the status of the operation.

• Journal of Korea Multimedia Society
• /
• v.6 no.3
• /
• pp.488-495
• /
• 2003

With the development of networks, multimedia communication has expanded its application field. From the remote control for household electric appliances to medicine, games, video conferencing and multimedia chatting, multimedia communication is being used in all parts of our lives. This multimedia communication requires the transmission of a lot of data at high speed. But if the transmission rate of the communication network exceeds the processing speed of being used in the high speed network environment, a bottleneck occurs in each node and deteriorates the performance of the network. This is the main reason for the slow speed of data transmission and packet loss. In this paper, considering the client's processing performance, reception performance was predicted and the way of flow control was shown. The computing performance of relevant Processor and its performance was estimated through the actual implementation.

• Journal of the Korea Society of Computer and Information
• /
• v.17 no.8
• /
• pp.1-10
• /
• 2012

This paper proposes design space exploration methodology of many-core processors including multimedia specific instructions to support high-performance and low power ultrasound imaging for portable devices. To explore the impact of multimedia instructions, we compare programs using multimedia instructions and baseline programs with a same many-core processor in terms of execution time, energy efficiency, and area efficiency. Experimental results using a $256{\times}256$ ultrasound image indicate that programs using multimedia instructions achieve 3.16 times of execution time, 8.13 times of energy efficiency, and 3.16 times of area efficiency over the baseline programs, respectively. Likewise, programs using multimedia instructions outperform the baseline programs using a $240{\times}320$ image (2.16 times of execution time, 4.04 times of energy efficiency, 2.16 times of area efficiency) as well as using a $240{\times}400$ image (2.25 times of execution time, 4.34 times of energy efficiency, 2.25 times of area efficiency). In addition, we explore optimal PE architecture of many-core processors including multimedia instructions by varying the number of PEs and memory size.

• Journal of Korea Multimedia Society
• /
• v.3 no.3
• /
• pp.309-319
• /
• 2000

The purpose of a parallel scheduling under a multiprocessor environment is to carry out the scheduling with the minimum synchronization overhead, and to perform load balance for a parallel application program. The processors calculate the chunk of iteration and are allocated to carry out the parallel iteration. At this time, it frequently accesses mutually exclusive global memory so that there are a lot of scheduling overhead and bottleneck imposed. And also, when the distribution of the parallel iteration in the allocated chunk to the processor is different, the different execution time of each chunk causes the load imbalance and badly affects the capability of the all scheduling. In the paper. we investigate the problems on the conventional algorithms in order to achieve the minimum scheduling overhead and load balance. we then present a new parallel loop scheduling algorithm, considering the locality of the data and processor affinity.

• Journal of Korea Multimedia Society
• /
• v.13 no.9
• /
• pp.1322-1328
• /
• 2010

Recently, keyword spotting system is greatly in the limelight as UI(User Interface) technology of ubiquitous home network system. Keyword spotting system is vulnerable to non-stationary noises such as TV, radio, dialogue. Especially, speech recognition rate goes down drastically under the embedded DSP(Digital Signal Processor) environments because it is relatively low in the computational capability to process input speech in real-time. In this paper, we propose a new keyword spotting system using the call-command method, which is consisted of small number of recognition networks. We select the call-command such as 'narae', 'home manager' and compose the small network as a token which is consisted of silence with the noise and call commands to carry the real-time recognition continuously for input speeches.

• Journal of Korea Multimedia Society
• /
• v.9 no.9
• /
• pp.1247-1256
• /
• 2006

VM(Virtual Machine) can be considered as a software processor which interprets the abstract machine code. Also, it is considered as a conceptional computer that consists of logical system configuration. But, the execution speed of VM system is much slower than that of a real processor system. So, it is very important to optimize the code for virtual machine to enhance the execution time. In this paper, we designed and implemented the optimizer for the virtual(or abstract) machine code(VMC) which is actually SIL(Standard Intermediate Language) that is an intermediate code of EVM(Embedded Virtual Machine). The optimizer uses the pattern matching optimization techniques reflecting the characteristics of the VMC as well as adopting the existing optimization methodology. Also, we tried a benchmark test for the VMC optimizer and obtained reasonable results.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.21 no.2
• /
• pp.99-105
• /
• 2007

In this paper, diskless personal multimedia player(PMP) that can access and decode the remote large multimedia data is implemented via wireless network. To implement this, WLAN based NFS protocol is used to connect PMP to the remote server and text image and movie files are decoded and played using ARM9 cored PXA255 embedded processor and Linux OS. The fuction and performance of the PMP is evaluated and verified using variuos types of contents. Linux kernel elements are configured and built in according to the hardware and software on the target board to install on the target board. The confirming result shows the required functions and performances.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.13 no.4
• /
• pp.139-149
• /
• 2003

In this paper a hardware design of area-efficient hash processor which implements MD5 algorithm using hardware sharing and carry-save addition schemes is described. To reduce area, the processor adopts hardware sharing scheme in which 1 step operation is divided into 2 substeps and then each substep is executed using the same hardware. Also to increase clock frequency, three serial additions of substep operation are transformed into two carry-save additions and one carry propagation addition. The MD5 hash processor is designed using 0.25 $\mu\textrm{m}$CMOS technology and consists of about 13,000 gates. From timing simulation results, the designed MD5 hash processor has 465 Mbps hash rates for 512-bit input message data under 120 MHz operating frequency.