• Journal of Korea Multimedia Society
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• v.11 no.6
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• pp.816-827
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• 2008

In this paper, two-stage pipelined floating-point arithmetic unit (FP-AU) is designed. The FP-AU processor supports seventeen operations to apply 3D graphics processor and has area-efficient and low-latency architecture that makes use of modified dual-path computation scheme, new normalization circuit, and modified compound adder based on flagged prefix adder. The FP-AU has about 4-ns delay time at logic synthesis condition using $0.18{\mu}m$ CMOS standard cell library and consists of about 5,930 gates. Because it has 250 MFLOPS execution rate and supports saturated arithmetic including a number of graphics-oriented operations, it is applicable to mobile 3D graphics accelerator efficiently.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.116-126
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• 2011

In this paper, we present a multi-media processor which can decode multiple-format video standards. The designed processor is evaluated with optimized MPEG-2, MPEG-4, and AVS (Audio video standard). There are two approaches for developing of real-time video decoders. First, hardware-based system is much superior to a processor-based one in execution time. However, it takes long time to implement and modify hardware systems. On the contrary, the software-based video codecs can be easily implemented and flexible, however, their performance is not so good for real-time applications. In this paper, in order to exploit benefits related to two approaches, we designed a processor called ASIP(Application specific instruction-set processor) for video decoding. In our work, we extracted eight common modules from various video decoders, and added several multimedia instructions to the processor. The developed processor for video decoders is evaluated with the Synopsys platform simulator and a FPGA board. In our experiment, we can achieve about 37% time saving in total decoding time.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.329-332
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• 1999

Currently, the most important technology is compression methods in the multimedia society. In audio compression, the method using human auditory nervous property is used. This method using psychoacoustical model is applied to perceptual audio coding, because human's audibility is limited. MPEG-II AAC(Advanced Audio Coding) is the most advanced coding scheme that is of benefit to high quality audio coding. The compression ratio is 1.4 times compared with MPEG-I layer-III. In this paper, the vector processor for MDCT/IMDCT(Modified Discrete Cosine Transform /Inverse Modified Discrete Cosine Transform) of MPEG-II AAC is designed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.55-64
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• 2004

In this paper, we propose an efficient FFT algorithm for high speed multimedia communication systems, and present its pipeline implementation results. Since the proposed algorithm is based on the radix-4 butterfly unit, the processing rate can be twice as fast as that based on the radix-2$^3$ algorithm. Also, its implementation is more area-efficient than the implementation from conventional radix-4 algorithm due to reduced number of nontrivial multipliers like using the radix-23 algorithm. In order to compare the proposed algorithm with the conventional radix-4 algorithm, the 64-point MDC pipelined FFT processor based on the proposed algorithm was implemented. After the logic synthesis using 0.6${\mu}{\textrm}{m}$ technology, the logic gate count for the processor with the proposed algorithm is only about 70% of that for the processor with the conventional radix-4 algorithm. Since the proposed algorithm can be achieve higher processing rate and better efficiency than the conventional algorithm, it is very suitable for the high speed multimedia communication systems such as WLAN, DAB, DVB, and ADSL/VDSL systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.80-85
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• 2011

The mount of network traffic from the Internet is increasing because of the use of Broadband Convergence Networks(BcN). Network traffic is also increasing because of the development of application, especially multimedia traffic from IPTV, VOD, and online games. This multimedia traffic not only has a huge payload but also should be considered a threat in real time. For this reason, this study examines the ways that routers distribute the bandwidth in accordance to traffic properties. To classify the property of the traffic, it is essential to analyze the application layer. However, the general network processor architecture serially processes the L2-4 and L7 layer. We propose a novel parallel network processor architecture with a global cache that processes L2-4 and L7 in parallel. To verify the proposed architecture, we simulated both of the architecture with SystemC. EEMBC and SNORT was used to measure L2-4 and L7 processing time. When multimedia traffic was entered into the network processor in the same flow, the proposed architecture showed about 85% higher performance than general architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.5
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• pp.916-924
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• 2003

Fair queueing has been an important issue in the multimedia networks where resources are shared among nodes both wired and wireless. In most fair queuing algorithms, based on the generalized processor sharing(GPS), emphasizes fairness guarantee while overlooking bounded delay guarantee which is critical to support multimedia services in the networks. In this paper, we propose a new fair queueing scheme, delay guaranteed fair queueing (DGFQ), which guaranteeing bounded delay of flows according to their individual delay requirements for multimedia services in the wireless packet networks.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.927-930
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• 2006

While Intel has been increasing its exclusive possession in the system IC semiconductor market, IBM, Sony, and Toshiba founded an alliance to develop the next entertainment multi-core processor, which is named CELL. Cell is designed upon the Power architecture and includes 8 SPE (Synergistic processor Element) cores for data handling, and supports SIMD architecture for optimal execution of multimedia, or game applications. Also, it includes expanded Power microarchitecture. In this paper, we analyzed and researched the Cell microprocessor, which is evaluated as the most powerful processor in this era.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.44-55
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• 2001

MAC(Multiply and ACcumulate) is the core operation of multimedia data processing. Because MAC units implemented on traditional DSP units or embedded processors have latency of three cycles and cannot operate on multiple data simultaneously, then, performances are seriously limited. Many high end general purpose microprocessors have SIMD MAC unit as a functional unit. But these high end MAC units must support pipeline structure for various operation modes and high clock frequency, which makes control logic complex and increases chip area. In this paper, a 64bit SIMD MAC unit for embedded processors is designed. It is implemented to have a latency of one clock cycle to remove pipeline control logics and a minimal area overhead for SIMD support is added to existing Booth multipliers.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1685-1688
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• 2003

The modem multimedia applications which are video Processor, video conference or video phone and so forth require real time processing. Because of a large amount of image data, those require high compression performance. In this paper, the proposed image processing encoder was designed by using wavelet transform encoding. The proposed filter block can process image data on tile high speed because of composing individual function blocks by parallel and compute both highpass and lowpass coefficient in the same clock cycle. When image data is decomposed into multiresolution, the proposed scheme needs external memory and controller to save intermediate results and it can operate within 33㎒.

• Proceedings of the Korea Multimedia Society Conference
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• 1998.04a
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• pp.355-360
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• 1998

병렬처리 컴퓨터는 하드웨어, 소프트웨어적인 두 가지 측면에서 동시에 만족되어질 때 최적의 성능 향상을 가져올 수 있다. 본 연구는 다양한 토폴로지를 제공하고 가격대 성능비가 좋은 트랜스퓨터상에서 자료간 종속 관계에 있는 병렬 코드를 수행하는 방법들을 소프트웨어적인 기법을 통해 알아보고 종속 관계에 있는 자료 처리 시 프로세서 수의 증가를 통한 속도향상을 실험하였다. 그 결과 본 논문에서 제시한 코드로 자료의 교환량을 최소화하기 위한 기법인 경우 프로세서의 수가 2개 일 때 cost-effective임을 제시하였다. 따라서 트랜스퓨터에서 효율적인 병렬 처리를 위해서는 각 node의 토폴로지, 자료분산 모델, processor의 개수들이 반드시 고려되어야 한다.