• Journal of the Institute of Convergence Signal Processing
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• v.6 no.2
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• pp.95-99
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• 2005

This paper presents an accurate recovery method of the reference clock which is needed for network synchronization in two-way satellite multimedia systems compliant with DVB-RCS specification and which use closed loop method for burst synchronization. In these systems, the remote station transmits TDMA burst via return link. For burst synchronization, it obtains reference clock from program clock reference (PCR) defined by MPEG-2 system specification. The PCR is generated periodically at the hub system by sampling system clock which runs at 27MHz $\pm$ 30ppm. Since the reference clock is recovered by means of digital PLL(DPLL) using imprecise PCR values due to variable random jitter, the recovered clock frequency of remote station doesn't exactly match reference clock of hub station. We propose a robust recovery method of reference clock against random delay jitter The simulation results show that the recovery error is remarkably decreased from 5 clocks to 1 clock of 27MHz relative to the general DPLL recovery method.

• Journal of Korea Multimedia Society
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• v.8 no.10
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• pp.1403-1410
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• 2005

The synchronization problem is directly related to the quality of service in multimedia communication and especially in real-time communication. In this study, we found the cause of clock fluctuation between encoder and decoder in MPEG-2 system layer was that the standard decoder design only considered a fixed time delay component. To solve it, we proposed Extended-SRTS algorithm, which uses STC as service clock by synchronizing transport stream. As the result, we can improve the effect of frequency-drift, time-varying-network-jitter and packing-jitter and so on And by virtue of this algorithm, we can make low the dependency of network clock, which makes easy to synchronize and connect transparently at the ends point, we expect the proposed algorithm can be widely applied to the field of real -time multimedia communications.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.11a
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• pp.335-342
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• 2000

멀티미디어 정보를 처리하기 위해서 필수적으로 필요한 기술이 멀티미디어 동기화를 구성하는 것이다. 본 논문에서는 두 시스템 사이의 클럭 동기를 맞추어 주기 위하여 가상 클럭(VGC : Virtual Global Clock)을 제안하였다. Loop flack 방법에 의한 제안된 가상 클럭은 통신이 가능한 모든 환경에 적용할 수 있다

• Journal of Korea Multimedia Society
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• v.10 no.3
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• pp.348-357
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• 2007

One of the major issues in recent researches on wireless sensor networks is to reduce energy consumption of sensor nodes operating with limited battery power, in order to lengthen their lifespan. Among the researches, we are interested in the schemes in which a sensor node periodically turns on and off its radio and requires information on the time when its neighbors will wake up (or turn on). Clock synchronization is essential for wakeup scheduling in such schemes. This paper proposes three methods based on the asynchronous averaging algorithm for clock synchronization in sensor nodes which periodically wake up: (1) a fast clock synchronization method during an initial network construction period, (2) a periodic clock synchronization method for saving energy consumption, and (3) a decision method for switching the operation mode of sensor nodes between the two clock synchronization methods. Through simulation, we analyze maximum clock difference and the number of messages required for clock synchronization.

• The Journal of the Korea Contents Association
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• v.12 no.5
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• pp.62-69
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• 2012

The newly developed field of media art is quickly making progress to include various and up-to-date forms of expression. Unlike in traditional art, the communication between the art and the viewer has become vastly important, in which the viewer is an active agent who participates and interacts with the artwork. These digital artworks can now be readily observed in everyday places and things, rather than being confined solely in the gallery space. By encouraging open interaction with the public, media art has become more accessible. Accordingly, this thesis examines the construction of a real-time multimedia clock piece using particle systems. Time has always been a significant theme in the realm of traditional art, which continues to be explored extensively in various forms of expression. In an attempt to express the continuity of time and the state of being value of existence based on technological skills, the thesis presents an artwork that uses the popular medium of a clock while also providing both usability and emotional satisfaction for the viewer's sensibility through interaction.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.10-17
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• 2012

This paper presents a clock regenerator using two $2^{nd}$ order ${\sum}-{\Delta}$ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different ${\sum}-{\Delta}$ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 ${\mu}m$ CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1351-1361
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• 1999

The wide spread of multimedia system demands a large area viewing display device which can inform a message to many people in open area. This paper is about the design of a large area viewing LED panel control system. The control system runs on 16 bit microprocessor MC68EC000 and has following functions: 16 line clock and time, 2 channel priority interrupt, 2 channel direct memory access, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16 byte FIFO, IBM PC/AT compatible keyboard interface, ISA bus, battery backuped real time clock, battery backuped 256 byte SRAM and watch dog timer. The core circuits are implemented to ASIC, considering lower cost, higher reliability, higher performance, smaller dimension, and lower power consumption. This is verified by simulation and fabricated in 0.6 um CMOS SOG processes. The total gate count is 39,083 and the clock frequency is 48 MGz. The fabricated ASIC is mounted on test board.

• Journal of Multimedia Information System
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• v.6 no.1
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• pp.7-14
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• 2019

This work presents a virtual prototyping design approach for an area-based image stitching hardware. The virtual hardware obtained from virtual prototyping is equivalent to the conceptual algorithm, yet the conceptual blocks are linked to the actual circuit components including the memory, logic gates, and arithmetic units. Through the proposed method, the overall structure, size, and computation speed of the actual hardware can be estimated in the early design stage. As a result, the optimized virtual hardware facilitates the hardware implementation by eliminating trail design and redundant simulation steps to optimize the hardware performance. In order to verify the feasibility of the proposed method, the virtual hardware of an image stitching platform has been realized, where it required 10,522,368 clock cycles to stitch two $1280{\times}1024$ sized images. Furthermore, with a clock frequency of 250MHz, the estimated computation time of the proposed virtual hardware is 0.877sec, which is 10x faster than the software-based image stitch platform using MATLAB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.11
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• pp.1130-1137
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• 2009

This paper proposes a new clock routing design for suppressing clock harmonic effects in a Printed Circuit Board (PCB) for a terrestrial Digital Multimedia Broadcasting(DMB) system. Typical crystal reference frequencies that are widely used in DMB tuners are 16.384 MHz, 19.2 MHz, 24.576 MHz. When the high-order harmonic components of these reference frequencies fall near the RF channel frequencies, receiver sensitivity of the tuners is seriously degraded. In this work, we propose a new clock routing design in order to address the clock harmonic coupling issue. The proposed design incorporates two inductors for isolating the clock ground from the main ground, and adopts a new strip line-style routing instead of the conventional microstrip line style routing to minimize the overlap area with the main ground. As a result, the RF sensitivity of the T-DMB tuner is improved by 2 dB.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1685-1688
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• 2003

The modem multimedia applications which are video Processor, video conference or video phone and so forth require real time processing. Because of a large amount of image data, those require high compression performance. In this paper, the proposed image processing encoder was designed by using wavelet transform encoding. The proposed filter block can process image data on tile high speed because of composing individual function blocks by parallel and compute both highpass and lowpass coefficient in the same clock cycle. When image data is decomposed into multiresolution, the proposed scheme needs external memory and controller to save intermediate results and it can operate within 33㎒.