• Title/Summary/Keyword: Multi-stacked

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IC Interposer Technology Trends

  • Min, Byoung-Youl
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2003.09a
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    • pp.3-17
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    • 2003
  • .Package Trend -> Memory : Lighter, Thinner, Smaller & High Density => SiP, 3D Stack -> MPU : High Pin Counts & Multi-functional => FCBGA .Interposer Trend -> Via - Unfilled Via => Filled Via - Staggered Via => Stacked Via -> Emergence of All-layer Build-up Processes -> Interposer Material Requirement => Low CTE, Low $D_{k}$, Low $D_{f}$, Halogen-free .New Technology Concept -> Embedded Passives, Imprint, MLTS, BBUL etc.

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Scheduling Methodology for MCP(Multi-chip Package) with Layer Sequence Constraint in Semiconductor Package (반도체 Package 공정에서 MCP(Multi-chip Package)의 Layer Sequence 제약을 고려한 스케쥴링 방법론)

  • Jeong, Young-Hyun;Cho, Kang-Hoon;Choung, You-In;Park, Sang-Chul
    • Journal of the Korea Society for Simulation
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    • v.26 no.1
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    • pp.69-75
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    • 2017
  • An MCP(Multi-chip Package) is a package consisting of several chips. Since several chips are stacked on the same substrate, multiple assembly steps are required to make an MCP. The characteristics of the chips in the MCP are dependent on the layer sequence. In the MCP manufacturing process, it is very essential to carefully consider the layer sequence in scheduling to achieve the intended throughput as well as the WIP balance. In this paper, we propose a scheduling methodology considering the layer sequence constraint.

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.2
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Layer Controlled Synthesis of Graphene using Two-Step Growth Process

  • Han, Jaehyun;Yeo, Jong-Souk
    • Proceedings of the Korean Vacuum Society Conference
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    • 2015.08a
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    • pp.221.2-221.2
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    • 2015
  • Graphene is very interesting 2 dimensional material providing unique properties. Especially, graphene has been investigated as a stretchable and transparent conductor due to its high mobility, high optical transmittance, and outstanding mechanical properties. On the contrary, high sheet resistance of extremely thin monolayer graphene limits its application. Artificially stacked multilayer graphene is used to decrease its sheet resistance and has shown improved results. However, stacked multilayer graphene requires repetitive and unnecessary transfer processes. Recently, growth of multilayer graphene has been investigated using a chemical vapor deposition (CVD) method but the layer controlled synthesis of multilayer graphene has shown challenges. In this paper, we demonstrate controlled growth of multilayer graphene using a two-step process with multi heating zone low pressure CVD. The produced graphene samples are characterized by optical microscope (OM) and scanning electron microscopy (SEM). Raman spectroscopy is used to distinguish a number of layers in the multilayer graphene. Its optical and electrical properties are also analyzed by UV-Vis spectrophotometer and probe station, respectively. Atomic resolution images of graphene layers are observed by high resolution transmission electron microscopy (HRTEM).

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Stacked Artificial Muscle Actuator Based on Dielectric Elastomer (고분자 유전 탄성체를 이용한 적층형 인공 근육 구동기)

  • Kwon, Hyeok-Yong;Ahn, Kwang-Jun;Kim, Dae-Gyeong;Lee, Hyung-Seok;Nguyen, Canh Toan;Koo, Ja-Choon;Moon, Hyung-Pil;Nam, Jae-Do;Choi, Hyouk-Ryeol
    • Journal of the Korean Society for Precision Engineering
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    • v.28 no.11
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    • pp.1234-1241
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    • 2011
  • In this work the potential, and the perspectives of the dielectric elastomer actuator are overviewed briefly. As an exemplary work, we introduce a novel contractile artificial muscle actuator based on Synthetic Elastomer(SE). SE is the name of new dielectric elastomer material we have developed and its synthesis procedures and evaluations are described in the first. The contractile artificial muscle actuator is made by stacking the actuator unit one by one along the in thickness direction and finished up by bonding the multi-stacked actuator. Its possibility for the robotic actuator is discussed and demonstrated via experiments.

A study on the bottom oxide scaling for dielectric in stacked capacitor using L/L vacuum system (L/L 진공시스템을 이용한 적층캐패시터의 하층산화막 박막화에 대한 연구)

  • 정양희;김명규
    • Electrical & Electronic Materials
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    • v.9 no.5
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    • pp.476-482
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    • 1996
  • The multi-dielectric layer SiO$_{2}$/Si$_{3}$N$_{4}$/SiO$_{2}$(ONO) is used to improve electrical capacitance and to scale down the memory device. In this paper, improvement of the capacitance by reducing the bottom oxide thickness in the nitride deposition with load lock(L/L) vacuum system is studied. Bottom oxide thickness under the nitride layer is measured by ellipsometer both in L/L and non-L/L systems. Both results are in the range of 3-10.angs. and 10-15.angs., respectively, independent of the nitride and top oxide thickness. Effective thickness and cell capacitance for SONOS capacitor are in the range of 50-52.angs. and 35-37fF respectively in the case of nitride 70.angs. in L/L vacuum system. Compared with non-L/L system, the bottom oxide thickness in the case of L/L system decreases while cell capacitance increases about 4 fF. The results obtained in this study are also applicable to ONO scaling in the thin bottom oxide region of memory stacked capacitor.

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Electrical characteristic of stacked $SiO_2/ZrO_2$ for nonvolatile memory application as gate dielectric (비휘발성 메모리 적용을 위한 $SiO_2/ZrO_2$ 다층 유전막의 전기적 특성)

  • Park, Goon-Ho;Kim, Kwan-Su;Oh, Jun-Seok;Jung, Jong-Wan;Cho, Won-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.134-135
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    • 2008
  • Ultra-thin $SiO_2/ZrO_2$ dielectrics were deposited by atomic layer chemical vapor deposition (ALCVD) method for non-volatile memory application. Metal-oxide-semiconductor (MOS) capacitors were fabricated by stacking ultra-thin $SiO_2$ and $ZrO_2$ dielectrics. It is found that the tunneling current through the stacked dielectric at the high voltage is lager than that through the conventional silicon oxide barrier. On the other hand, the tunneling leakage current at low voltages is suppressed. Therefore, the use of ultra-thin $SiO_2/ZrO_2$ dielectrics as a tunneling barrier is promising for the future high integrated non-volatile memory.

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Fabrication of coated conductor stacked multi-filamentary wire (적층형 초전도 다심 선재 제조)

  • Yun, K.S.;Ha, H.S.;Oh, S.S.;Moon, S.H.;Kim, C.J.
    • Progress in Superconductivity and Cryogenics
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    • v.14 no.1
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    • pp.4-7
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    • 2012
  • Coated conductors have been developed to increase piece length and critical current for electric power applications. Otherwise, Many efforts were carried out to reduce AC loss of coated conductor for AC applications. Twisting and cabling processes are effective to reduce AC loss but, these processes can not be applied for tape shaped coated conductor. It is inevitable to have thin rectangular shape because coated conductor is fabricated by thin film deposition process on metal substrate. In this study, round shape superconducting wire was first fabricated using coated conductors. First of all, Ag coated conductor was used. coated conductor was slitted to several wires with narrow width below 1mm. 12ea slitted wires were parallel stacked on top of another until making up the square cross-section. The bundle of coated conductors was heat treated to stick on each other by diffusion bonding and then copper plated to make round shape wire. Critical current of round wire was measured 185A at 77K, self field.

Fabrication of Micro-/Nano- Hybrid 3D Stacked Patterns (나노-마이크로 하이브리드 3차원 적층 패턴의 제조)

  • Park, Tae Wan;Jung, Hyunsung;Bang, Jiwon;Park, Woon Ik
    • Journal of the Korean institute of surface engineering
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    • v.51 no.6
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    • pp.387-392
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    • 2018
  • Nanopatterning is one of the essential nanotechnologies to fabricate electronic and energy nanodevices. Therefore, many research group members made a lot of efforts to develop simple and useful nanopatterning methods to obtain highly ordered nanostructures with functionality. In this study, in order to achieve pattern formation of three-dimensional (3D) hierarchical nanostructures, we introduce a simple and useful patterning method (nano-transfer printing (n-TP) process) consisting of various linewidths for diverse materials. Pt and $WO_3$ hybrid line structures were successfully stacked on a flexible polyimide substrate as a multi-layered hybrid 3D pattern of Pt/WO3/Pt with line-widths of $1{\mu}m$, $1{\mu}m$ and 250 nm, respectively. This simple approach suggests how to fabricate multiscale hybrid nanostructures composed of multiple materials. In addition, functional hybrid nanostructures can be expected to be applicable to various next-generation electronic devices, such as nonvolatile memories and energy harvesters.

Structural Characteristics on InAs Quantum Dots multi-stacked on GaAs(100) Substrates

  • Roh, Cheong-Hyun;Park, Young-Ju;Kim, Eun-Kyu;Shim, Kwang-Bo
    • Journal of the Microelectronics and Packaging Society
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    • v.7 no.1
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    • pp.25-28
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    • 2000
  • The InAs self-assembled quantun dots (SAQDS) were grown on a GaAs(100) substrate using a molecular beam epitaxy (MBE) technique. The InAs QDs were multi-stacked to have various layer structures of 1, 3, 6, 10, 15 and 20 layers, where the thickness of the GaAs spacer and InAs QD layer were 20 monolayers (MLs) and 2 MLs, respectively. The nanostructured feature was characterized by photoluminescence (PL) and scanning transmission electron microscopy (STEM). It was found that the highest PL intensity was obtained from the specimen with 6 stacking layers and the energy of the PL peak was split with increasing the number of stacking layers. The STEM investigation exhibited that the quantum dots in the 6 stacking layer structure were well aligned in vertical columns without any deflect generation, whereas the volcano-like deflects were formed vertically along the growth direction over 10 periods of InAs stacking layers.

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