• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1336-1338
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• 2000

This paper proposed the single phase multi-level PWM AC/DC converter using binary combine which controls input current by combining buck converters to improve input current characteristic, and confirmed its validity throughout simulation and experiment. This method, which is multiplying and duplicating output of converter of equal capacity, has the advantage of being able to control unit power factor of input current and reducing of the problem caused by high frequency switching, and appling to high power converter because filter is not necessary etc.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.3
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• pp.258-266
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• 2012

This paper describes a biped walking algorithm for a hydraulic humanoid robot on inclined floors. To realize stable and robust biped walking, the walking algorithm was divided into five control strategies. The first is a joint position control strategy. This strategy is for tracking desired joint position trajectories with a gain switching. The second is a multi-model based ZMP (Zero Moment Point) control strategy for dynamic balance. The third is a walking pattern flow control strategy for smooth transition from step to step. The fourth is an ankle compliance control, which increases the dynamic stability at the moment of floor contact. The last is an upright pose control strategy for robust walking on an inclined floor. All strategies are based on simple pendulum models and include practical sensory feedback in order to implement the strategies on a physical robot. Finally, the performance of the control strategies are evaluated and verified through dynamic simulations of a hydraulic humanoid on level and inclined floors.

• Journal of Korea Society of Digital Industry and Information Management
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• v.4 no.3
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• pp.77-83
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• 2008

In this paper, CPLD low power technology mapping for reuse module design under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.45-46
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• 2012

본 논문에서는 멀티레벨 인버터에서 발생하는 DC Link 단의 커패시터 불 평형 문제를 해결하고자 새로운 DC 전압 균형을 위한 스위칭 방식에 대해 제안한다. 제안한 방식은 DC-Link 단에 위치한 각각의 커패시터들의 전압을 센싱하고 이를 PI제어를 통해 스위칭 신호를 제어함으로써 각각의 커패시터에 걸리는 전압을 균일하게 만듦으로써, 커패시터단의 전압 불 평형을 개선하였으며, 이를 3상 2레벨 멀티-레벨 인버터를 이용한 시뮬레이션 결과를 통해 본 논문의 타당성을 검증하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.1
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• pp.59-65
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• 2021

This study proposes a dead-time implementation method suitable for cell voltage control of a cascaded H-bridge (CHB) inverter. The PWM module of an existing microcontroller cannot generate a maximum voltage due to the dead-time effect when used as the cell controller of the CHB inverter. In the proposed method, the operation method of the PWM module was changed without using the dead time module included in the existing microcontroller, so that the cell output voltage can be increased to the maximum voltage without voltage discontinuity. During the maximum voltage generation period, the full turn-on state can be maintained without unnecessary switching. The validity of the proposed method is confirmed through an experiment.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1380-1391
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• 2015

This paper provides a loss analysis and comparison of high power semiconductor devices in 5MW Permanent Magnet Synchronous Generator (PMSG) Medium Voltage (MV) Wind Turbine Systems (WTSs). High power semiconductor devices of the press-pack type IGCT, module type IGBT, press-pack type IGBT, and press-pack type IEGT of both 4.5kV and 6.5kV are considered in this paper. Benchmarking is performed based on the back-to-back type 3-level Neutral Point Clamped Voltage Source Converters (3L-NPC VSCs) supplied from a grid voltage of 4160V. The feasible number of semiconductor devices in parallel is designed through a loss analysis considering both the conduction and switching losses under the operating conditions of 5MW PMSG wind turbines, particularly for application in offshore wind farms. This paper investigates the loss analysis and thermal performance of 5MW 3L-NPC wind power inverters under the operating conditions of various power factors. The loss analysis and thermal analysis are confirmed through PLECS Blockset simulations with Matlab Simulink. The comparison results show that the press-pack type IGCT has the highest efficiency including the snubber loss factor.

• Journal of Power Electronics
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• v.11 no.2
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• pp.132-139
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• 2011

The selective harmonic elimination pulse width modulation (SHEPWM) switching strategy has been applied to multilevel inverters to remove low harmonics. Naturally, the related equations do not have feasible solutions for some operating points associated with the modulation index (M). However, with these infeasible points, minimizing instead of eliminating harmonics is performed. Thus, harmful harmonics such as the $5^{th}$ harmonic still remains in the output waveform. Therefore, it is proposed in this paper to ignore solving the equation associated with the highest order harmonics. A reduction in the eliminated harmonics results in an increase in the degrees of freedom. As a result, the lower order harmonics are eliminated in more operating points. A 9-level inverter is chosen as a case study. The genetic algorithm (GA) for optimization purposes is used. Simulation results verify the proposed method.

• Proceedings of the Korea Water Resources Association Conference
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• 2022.05a
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• pp.85-85
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• 2022

The world's most extensive and active deltas, Louisiana's wetlands, are deteriorating rapidly due to multiple stressors such as the discharge of the Mississippi River, sea-level rise, and coastal retreat, the substantial but spatially and temporally variable impacts. However, the ecological and anthropogenic histories, the mode of environmental changes on a multi-millennial timescale have not been thoroughly documented. This study, a palynology-based multiproxy analysis, investigates hydrological, geological, geochemical, and anthropogenic impacts on southern Louisiana wetlands and a variety of external forcing agents influencing ecological succession. Sediment cores extracted from a small pond on a mangrove-dominate island near Port Fourchon, Louisiana, USA yielded a 4,000-year record. The site has been transformed from freshwater to saline water environments, to a mangrove dominant island over the late Holocene. The multivariate principal component analysis identified the relative strength of external drivers responsible for each ecological shift. The Mississippi River delta cycle (lobe switching) was the dominant driver of ecosystem changes during the late Holocene, while relative sea-level rise, tropical cyclones, climate, and anthropogenic effects have been the main drivers late in the site's history.

• Nanomaterials
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• v.12 no.22
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• pp.4096-4107
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• 2022

In this work, a hybrid-phase transition field-effects-transistor (hyper-FET) integrated with phase-transition materials (PTM) and a multi-nanosheet FET (mNS-FET) at the 3 nm technology node were analyzed at the device and circuit level. Through this, a benchmark was performed for presenting device design guidelines and for using ultra-low-power applications. We present an optimization flow considering hyper-FET characteristics at the device and circuit level, and analyze hyper-FET performance according to the phase transition time (TT) and baseline-FET off-leakage current (I_OFF) variations of the PTM. As a result of inverter ring oscillator (INV RO) circuit analysis, the optimized hyper-FET increases speed by +8.74% and reduces power consumption by -16.55%, with IOFF = 5 nA of baseline-FET and PTM TT = 50 ps compared to the conventional mNS-FET in the ultra-low-power region. As a result of SRAM circuit analysis, the read static noise margin is improved by 43.9%, and static power is reduced by 58.6% in the near-threshold voltage region when the PTM is connected to the pull-down transistor source terminal of 6T SRAM for high density. This is achieved at 41% read current penalty.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.1
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• pp.153-162
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• 2018

The importance of energy harvesting technique is increasing due to the elevated level of demand for sustainable power sources for wearable device applications. In this study, we developed an Energy Harvesting wearable Platform(EH-P) architecture which is used in the design of a multi-energy source based on TENG. The proposed switching circuit produces power with higher current at lower voltage from energy harvesting sources with lower current at higher voltage. This can powers microcontrollers for a short period of time by using PV and TENG complementarily placed under hard conditions for the sources such as indoors. As a result, the whole interface circuit is completely self-powered with this makes it possible to run of sensing on a Wearable device platform. It was possible to increase the wearable device life time by supplying more than 29% of the power consumption to wearable devices. The results presented in this paper show the potential of multi-energy harvesting platform for use in wearable harvesting applications, provide a means of choosing the energy harvesting source.