• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2002년도 Proceedings of the International Welding/Joining Conference-Korea
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• pp.320-323
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• 2002

This paper presents a new generation of system for pressure vessel and shipbuilding. Typical pressure vessel and ship building weld joint preparations are either traditional V, butt, fillet grooves or have narrow or semi narrow gap profiles. The fillet and U groove are prevalently used in heavy industries and shipbuilding to melt and join the parts. Since the wall thickness can be up to 6" or greater, welds must be made in many layers, each layer containing several passes. However, the welding time for the conventional processes such as SAW(Submerged Arc Welding) and FCAW(Flux Cored Arc Welding) can be many hours. Although SAW and FCAW are normally a mechanized process, pressure vessel and ship structures welding up to now have usually been controlled by a full time operator. The operator has typically been responsible for positioning each individual weld run, for setting weld process parameters, for maintaining flux and wire levels, for removing slag and so on. The aim of the system is to develop a high speed welding system with multitorch for increasing the production speed on the line and to remove the need for the operator so that the system can run automatically for the complete multi-torch multi-layer weld. To achieve this, a laser vision sensor, a rotating torch and an image processing algorithm have been made. Also, the multitorch welding system can be applicable for the fine grained steel because of the high welding speed and lower heat input compare to a conventional welding process.

• 한국산업정보학회논문지
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• 제25권1호
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• pp.25-30
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• 2020

3상 다층 고온 초전도 동축 케이블은 초전도 선재 사용량의 감소 및 케이블의 소형화와 같은 이점 때문에 활발히 연구되고 있다. 3상 다층 고온 초전도 동축 케이블의 전기적 특성은 기존 초전도 케이블과 차이를 가지므로 실제 시스템에 적용하기 위해 충분한 분석이 필요하다. 본 논문에서는 PSCAD/EMTDC 기반 시뮬레이션을 통하여 22.9 kV, 60 MVA급 3상 다층 고온 초전도 동축 케이블을 모델링하고 과도 특성을 분석하였다. 결과적으로 3상 다층 고온 초전도 동축 케이블에서 고장전류가 발생하면 대부분의 고장전류가 구리 포머층을 통해 우회한다. 이때, 케이블 전체 온도는 약 5 K 증가하였다. 본 논문을 통해 3상 다층 고온 초전도 동축 케이블의 과도 상태에 대한 신뢰성을 확인할 수 있으며 향후 케이블의 실 계통 적용에 도움이 될 수 있다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.235-235
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• 2003

The development of a buffer layer is an important issue for the second -generation wire, YBCO coated metal wire. The buffer layer demands not only on the prohibition of the reaction between YBCO and metal substrate, but also the proper lattice match and conductivity for high critical current density (Jc) of YBCO superconductor, In order to satisfy these demands, we suggested CaRuO3 as a useful candidate having that the lattice mismatches with Ni (200) and with YBCO are 8.2% and 8.0%, respectively. The CaRuO3 thin films were deposited on Ni substrates using various methods, such as e-beam evaporation and DC and RF magnetron sputtering. These films were investigated using SEM, XRD, pole-figure and AES. In e-beam evaporation, the deposition temperature of CaRuO3 was the most important since both hi-axial texturing and NiO formation between Ni and CaRuO3 depended on it. Also, the oxygen flow rate had i[n effect on the growth of CaRuO3 on Ni substrates. The optimal conditions of crystal growth and film uniformity were 400$^{\circ}C$, 50 ㎃ and 7 ㎸ when oxygen flow rate was 70∼100sccm In RF magnetron sputtering, CaRuO3 was deposited on Ni substrates with various conditions and annealing temperatures. As a result, the conductivity of CaRuO3 thin films was dependent on CaRuO3 layer thickness and fabrication temperature. We suggested the multi-step deposition, such as two-step deposition with different temperature, to prohibit the NiO formation and to control the hi-axial texture.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.104-106
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• 2003

다층의 산화물 박막으로 이루어진 coated conductor의 제조를 위하여 각층의 증착조건이 최적화되어야 한다. 가공/열처리를 통하여 2축배향성을 가지는 Ni 금속 기판위에 $Y_2O_3$, YSZ, $CeO_2$ 등의 산화물 완충층을 증착한 후 초전도층인 YBCO를 증착하였다. 12도와 8도의 in-plane fwhm (full width at half maximum)과 out-of-plane fwhm을 가지는 Ni 기판을 이용하여 13도와 4.5도의 in-plane 및 out-of-plane fwhm을 가지는 YBCO coated conductor를 제조하였다. 임계온도 (Tc), 임계전류 (Ic), 및 임계전류밀도 (Jc) 는 각각 84K, 3.3A, 및 $310,000\;A/cm^2$ 이었다.

• 전자공학회논문지
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• 제54권7호
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• pp.21-28
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• 2017

FPGA 배치 툴 연구는 학계에서도 단순한 가상 아키텍처 모델 가정에서 벗어나 상용 툴처럼 캐리체인이나 광폭함수 멀티플렉서, 메모리/승산기 블록 등의 성능 및 밀도를 향상시키는 소자들을 포함하는 현실적인 모델을 적용하기 시작하였다. 이 때 발생하는 실제적 이슈들을 다룬 사전 패킹, 다층 밀도 분석 등의 기법이 초기 분석적 배치 (Analytic Placement)에 적용되어 밀도를 분산시키면서 배선 길이를 효과적으로 최소화한 연구가 앞서 발표된 바 있다. 더 나아가 궁극적으로는 타이밍을 최적화해야하기 때문에 많은 연구에서는 타이밍 제약 조건을 만족시키기 위한 기법들이 제시되고 있다. 그러나 초기 배치 후 진행되는 배치 적법화 및 배치 개선에서 주로 적용될 뿐 분석적 배치에서 이러한 타이밍 기법을 적용한 사례는 거의 없다. 본 논문에서는 사전 패킹 및 다층 밀도 분석 등의 기법이 구현된 기존 분석적 배치에 타이밍 제약 조건 위반을 검출하고 이를 최소화하는 기법을 결합하는 방안을 소개한다. 먼저 정적 타이밍 검증기를 집적하여 배선 길이가 최소화된 기존 배치 결과의 타이밍을 검사해 보았으며 위반을 감소시키기 위해 신호 도착 시간 (Arrival Time)을 최소화하는 함수를 분석적 배치의 목적 함수에 추가하였다. 이 때 각 클록마다 주기가 다를 수 있기 때문에 각 클록별로 함수를 따로 계산해 합산하는 방안이 제안되었다. 또한, 위반이 없는 클록 도메인의 신호 경로들도 불필요하게 단축될 수 있기 때문에 음수 슬랙 (Negative Slack)을 계산하여 이를 최소화하는 함수를 추가로 제안하여 비교하였다. 영역 분할 기법 (Partitioning)을 기반으로 배선 길이를 최소화하는 기존 배치 적법화를 그대로 사용한 후 타이밍 검증을 통해 초기 분석적 배치 단계에서 타이밍 개선 효과를 분석하였다. 배치 적법화 시 추가적인 타이밍 최적화 기법이 사용되지 않았기 때문에 타이밍 개선이 있다면 이것은 전적으로 분석적 배치의 목적 함수개선에 의한 효과이다. 12개 실용예제에 대해 실험한 결과, 목적 함수에 도착 시간 함수가 적용되었을 때 그렇지 않았을 때보다 최악 음수 슬랙 (Worst Negative Slack)이 평균 약 15% 정도 감소되었으며 음수 슬랙 함수가 적용되었을 때 이보다 약 6%정도 추가로 더 감소됨을 확인하였다.

• 전자공학회논문지
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• 제51권10호
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• pp.96-106
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• 2014

기존 학계의 FPGA 툴 연구는 단순한 가상 아키텍처 모델 가정에 의존해 왔다. 이러한 제약을 극복하기 위한 첫걸음으로 분석적 배치 및 배치 적법화의 기본 알고리즘들을 상용 FPGA의 아키텍처에 적용하는 실제 상황에서 발생되는 이슈들을 도출하여 대안을 제시한 후 그 효과를 평가하였다. 먼저, 코어 사용률이 낮은 FPGA에서 배치된 셀들의 무게 중심이 칩 중심에서 벗어나는 현상이 발생할 수 있는데 이 변위를 최소화하는 함수를 분석적 배치의 목적 함수에 추가하였다. 또한 배치 밀도 평가의 정확도를 높이기 위해 셀 종류별로 별도의 밀도 행렬을 사용하는 다층 분석, 그리고 자원이 매우 한정된 블록의 조기 고정 방안을 제안하였다. 그밖에, 슬라이스 내에서 두 개의 플립플롭이 제어 핀들을 공유하기 때문에 발생하는 호환성 문제를 개선하기 위한 플립플롭 사전 패킹도 제안하였다. 제안된 기법은 상용 FPGA 아키텍처를 정확하게 모델링하고 수정 개선할 수 있는 K-FPGA 패브릭 평가 툴킷을 근간으로 구현되었으며 12개의 실용 예제에 적용하여 기존 방식에 비해 평균적으로 배선길이 22%, 슬라이스 사용량 5%를 감축하는 효과를 확인하였다. 본 연구는 신규 FPGA 아키텍처 개발을 위한 최적화 CAD 툴 개발 연구의 기초가 될 것으로 기대한다.

• 대한기계학회논문집B
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• 제27권8호
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• pp.1023-1032
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• 2003

The effect of local forcing on the separated flow over a backward-facing step is investigated through hot-wire measurements and flow visualization with multi-smoke wires. The boundary layer upstream of the separation point is laminar and the Reynolds number based on the free stream velocity and the step height is 13800. The local forcing is given from a slit located at the step edge and the forcing signal is always defined when the wind tunnel is in operation. In case of single frequency forcing, the streamwise velocity and the reattachment length are measured under forcing with various forcing frequencies. For the range of 0.010〈S $t_{\theta}$〈0.013, the forcing frequency component of the streamwise velocity fluctuation grows exponentially and is saturated at x/h = 0.75 , while its subharmonic component grows following the fundamental and is saturated at x/h = 2.0. However, the saturated value of the subharmonic is much lower than that of the fundamental. It is observed that the vortex formation is inhibited by the forcing at S $t_{\theta}$ = 0.019 . For double frequency forcing, natural instability frequency is adopted as a fundamental frequency and its subharmonic is superposed on it. The fundamental frequency component of the streamwise velocity grows exponentially and is saturated at 0.5 < x/ｈ < 0.75, while its subharmonic component grows following the fundamental and is saturated at x/ｈ= 1.5 . Furthermore, the saturated value of the subharmonic component is much higher than that for the single frequency forcing and is nearly the same or higher than that of the fundamental. It is observed that the subharmonic component does not grow for the narrow range of the initial phase difference. This means that there is a range of the initial phase difference where the vortex parring cannot be enhanced or amplified by double frequency forcing. In addition, this effect of the initial phase difference on the development of the shear layer and the distribution of the reattachment length shows a similar trend. From these observations, it can be inferred that the development of the shear layer and the reattachment length are closely related to the vortex paring.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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• pp.87-87
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• 2010

Photoelectrochemical (PEC) systems are promising methods of producing H2 gas using solar energy in an aqueous solution. The photoelectrochemical properties of numerous metal oxides have been studied. Among them, the PEC systems based on TiO2 have been extensively studied. However, the drawback of a PEC system with TiO2 is that only ultraviolet (UV) light can be absorbed because of its large band gap (3.2 - 3.4 eV). Two approaches have been introduced in order to use PEC cells in the visible light region. The first method includes doping impurities, such as nitrogen, into TiO2, and this technique has been extensively studied in an attempt to narrow the band gap. In comparison, research on the second method, which includes visible light water splitting in molecular photosystems, has been slow. Mallouk et al. recently developed electrochemical water-splitting cells using the Ru(II) complex as the visible light photosensitizer. the dye-sensitized PEC cell consisted of a dye-sensitized TiO2 layer, a Pt counter electrode, and an aqueous solution between them. Under a visible light (< 3 eV) illumination, only the dye molecule absorbed the light and became excited because TiO2 had the wide band gap. The light absorption of the dye was followed by the transfer of an electron from the excited state (S*) of the dye to the conduction band (CB) of TiO2 and its subsequent transfer to the transparent conducting oxide (TCO). The electrons moved through the wire to the Pt, where the water reduction (or H2 evolution) occurred. The oxidized dye molecules caused the water oxidation because their HOMO level was below the H2O/O2 level. Organic dyes have been developed as metal-free alternatives to the Ru(II) complexes because of their tunable optical and electronic properties and low-cost manufacturing. Recently, organic dye molecules containing multi-branched, multi-anchoring groups have received a great deal of interest. In this work, tri-branched tri-anchoring organic dyes (Dye 2) were designed and applied to visible light water-splitting cells based on dye-sensitized TiO2 electrodes. Dye 2 had a molecular structure containing one donor (D) and three acceptor (A) groups, and each ended with an anchoring functionality. In comparison, mono-anchoring dyes (Dye 1) were also synthesized. The PEC response of the Dye 2-sensitized TiO2 film was much better than the Dye 1-sensitized or unsensitized TiO2 films.

• 반도체디스플레이기술학회지
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• 제17권4호
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• pp.42-45
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• 2018

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.