• Proceedings of the KWS Conference
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• 2002.10a
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• pp.320-323
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• 2002

This paper presents a new generation of system for pressure vessel and shipbuilding. Typical pressure vessel and ship building weld joint preparations are either traditional V, butt, fillet grooves or have narrow or semi narrow gap profiles. The fillet and U groove are prevalently used in heavy industries and shipbuilding to melt and join the parts. Since the wall thickness can be up to 6" or greater, welds must be made in many layers, each layer containing several passes. However, the welding time for the conventional processes such as SAW(Submerged Arc Welding) and FCAW(Flux Cored Arc Welding) can be many hours. Although SAW and FCAW are normally a mechanized process, pressure vessel and ship structures welding up to now have usually been controlled by a full time operator. The operator has typically been responsible for positioning each individual weld run, for setting weld process parameters, for maintaining flux and wire levels, for removing slag and so on. The aim of the system is to develop a high speed welding system with multitorch for increasing the production speed on the line and to remove the need for the operator so that the system can run automatically for the complete multi-torch multi-layer weld. To achieve this, a laser vision sensor, a rotating torch and an image processing algorithm have been made. Also, the multitorch welding system can be applicable for the fine grained steel because of the high welding speed and lower heat input compare to a conventional welding process.

• Journal of Korea Society of Industrial Information Systems
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• v.25 no.1
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• pp.25-30
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• 2020

Three-phase multi-layer high temperature superconducting coaxial (TPMHTSC) cable is being actively studied due to advantages such as the reduction of the amount of superconducting wire usage and the miniaturization of the cable. The electrical characteristics of TPMHTSC cables differ from those of conventional superconducting cables, so sufficient analysis is required to apply them to the actual system. In this paper, the authors modeled 22.9 kV, 60 MVA TPMHTSC cable and analyzed the transient characteristics using a PSCAD/EMTDC-based simulation. As a result, when a fault current flows in TPMHTSC cable, most of the fault current is bypassed through the copper former layers. At this time, the total cable temperature increased by about 5 K. Through this study, we can verify the reliability of the TPMHTSC cable against the transient state, and it can be helpful for the practical application of the cable in the future.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.235-235
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• 2003

The development of a buffer layer is an important issue for the second -generation wire, YBCO coated metal wire. The buffer layer demands not only on the prohibition of the reaction between YBCO and metal substrate, but also the proper lattice match and conductivity for high critical current density (Jc) of YBCO superconductor, In order to satisfy these demands, we suggested CaRuO3 as a useful candidate having that the lattice mismatches with Ni (200) and with YBCO are 8.2% and 8.0%, respectively. The CaRuO3 thin films were deposited on Ni substrates using various methods, such as e-beam evaporation and DC and RF magnetron sputtering. These films were investigated using SEM, XRD, pole-figure and AES. In e-beam evaporation, the deposition temperature of CaRuO3 was the most important since both hi-axial texturing and NiO formation between Ni and CaRuO3 depended on it. Also, the oxygen flow rate had i[n effect on the growth of CaRuO3 on Ni substrates. The optimal conditions of crystal growth and film uniformity were 400$^{\circ}C$, 50 ㎃ and 7 ㎸ when oxygen flow rate was 70∼100sccm In RF magnetron sputtering, CaRuO3 was deposited on Ni substrates with various conditions and annealing temperatures. As a result, the conductivity of CaRuO3 thin films was dependent on CaRuO3 layer thickness and fabrication temperature. We suggested the multi-step deposition, such as two-step deposition with different temperature, to prohibit the NiO formation and to control the hi-axial texture.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.104-106
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• 2003

다층의 산화물 박막으로 이루어진 coated conductor의 제조를 위하여 각층의 증착조건이 최적화되어야 한다. 가공/열처리를 통하여 2축배향성을 가지는 Ni 금속 기판위에 $Y_2O_3$, YSZ, $CeO_2$ 등의 산화물 완충층을 증착한 후 초전도층인 YBCO를 증착하였다. 12도와 8도의 in-plane fwhm (full width at half maximum)과 out-of-plane fwhm을 가지는 Ni 기판을 이용하여 13도와 4.5도의 in-plane 및 out-of-plane fwhm을 가지는 YBCO coated conductor를 제조하였다. 임계온도 (Tc), 임계전류 (Ic), 및 임계전류밀도 (Jc) 는 각각 84K, 3.3A, 및 $310,000\;A/cm^2$ 이었다.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.21-28
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• 2017

Practical models for FPGA architectures which include performance- and/or density-enhancing components such as carry chains, wide function multiplexers, and memory/multiplier blocks are being applied to academic FPGA placement tools which used to rely on simple imaginary models. Previously the techniques such as pre-packing and multi-layer density analysis are proposed to remedy issues related to such practical models, and the wire length is effectively minimized during initial analytic placement. Since timing should be optimized rather than wire length, most previous work takes into account the timing constraints. However, instead of the initial analytic placement, the timing-driven techniques are mostly applied to subsequent steps such as placement legalization and iterative improvement. This paper incorporates the timing driven techniques, which check if the placement meets the timing constraints given in the standard SDC format, and minimize the detected violations, with the existing analytic placer which implements pre-packing and multi-layer density analysis. First of all, a static timing analyzer has been used to check the timing of the wire-length minimized placement results. In order to minimize the detected violations, a function to minimize the largest arrival time at end points is added to the objective function of the analytic placer. Since each clock has a different period, the function is proposed to be evaluated for each clock, and added to the objective function. Since this function can unnecessarily reduce the unviolated paths, a new function which calculates and minimizes the largest negative slack at end points is also proposed, and compared. Since the existing legalization which is non-timing driven is used before the timing analysis, any improvement on timing is entirely due to the functions added to the objective function. The experiments on twelve industrial examples show that the minimum arrival time function improves the worst negative slack by 15% on average whereas the minimum worst negative slack function improves the negative slacks by additional 6% on average.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.96-106
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• 2014

Previous academic research on FPGA tools has relied on simple imaginary models for the targeting architecture. As the first step to overcome such restriction, the issues on analytic placement and legalization which are applied to commercial FPGAs have been brought up, and several techniques to remedy them are presented, and evaluated. First of all, the center of gravity of the placed cells may be far displaced from the center of the chip during analytic placement. A function is proposed to be added to the objective function for minimizing this displacement. And then, the density map is expanded into multiple layers to accurately calculate the density distribution for each of the cell types. Early fixation is also proposed for the memory blocks which can be placed at limited sites in small numbers. Since two flip-flops share control pins in a slice, a compatibility constraint is introduced during legalization. Pre-packing compatible flip-flops is proposed as a proactive step. The proposed techniques are implemented on the K-FPGA fabric evaluation framework in which commercial architectures can be precisely modeled, and modified for enhancement, and validated on twelve industrial strength examples. The placement results show that the proposed techniques have reduced the wire length by 22%, and the slice usage by 5% on average. This research is expected to be a development basis of the optimization CAD tools for new as well as the state-of-the-art FPGA architectures.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.27 no.8
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• pp.1023-1032
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• 2003

The effect of local forcing on the separated flow over a backward-facing step is investigated through hot-wire measurements and flow visualization with multi-smoke wires. The boundary layer upstream of the separation point is laminar and the Reynolds number based on the free stream velocity and the step height is 13800. The local forcing is given from a slit located at the step edge and the forcing signal is always defined when the wind tunnel is in operation. In case of single frequency forcing, the streamwise velocity and the reattachment length are measured under forcing with various forcing frequencies. For the range of 0.010〈S $t_{\theta}$〈0.013, the forcing frequency component of the streamwise velocity fluctuation grows exponentially and is saturated at x/h = 0.75 , while its subharmonic component grows following the fundamental and is saturated at x/h = 2.0. However, the saturated value of the subharmonic is much lower than that of the fundamental. It is observed that the vortex formation is inhibited by the forcing at S $t_{\theta}$ = 0.019 . For double frequency forcing, natural instability frequency is adopted as a fundamental frequency and its subharmonic is superposed on it. The fundamental frequency component of the streamwise velocity grows exponentially and is saturated at 0.5 < x/ｈ < 0.75, while its subharmonic component grows following the fundamental and is saturated at x/ｈ= 1.5 . Furthermore, the saturated value of the subharmonic component is much higher than that for the single frequency forcing and is nearly the same or higher than that of the fundamental. It is observed that the subharmonic component does not grow for the narrow range of the initial phase difference. This means that there is a range of the initial phase difference where the vortex parring cannot be enhanced or amplified by double frequency forcing. In addition, this effect of the initial phase difference on the development of the shear layer and the distribution of the reattachment length shows a similar trend. From these observations, it can be inferred that the development of the shear layer and the reattachment length are closely related to the vortex paring.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.87-87
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• 2010

Photoelectrochemical (PEC) systems are promising methods of producing H2 gas using solar energy in an aqueous solution. The photoelectrochemical properties of numerous metal oxides have been studied. Among them, the PEC systems based on TiO2 have been extensively studied. However, the drawback of a PEC system with TiO2 is that only ultraviolet (UV) light can be absorbed because of its large band gap (3.2 - 3.4 eV). Two approaches have been introduced in order to use PEC cells in the visible light region. The first method includes doping impurities, such as nitrogen, into TiO2, and this technique has been extensively studied in an attempt to narrow the band gap. In comparison, research on the second method, which includes visible light water splitting in molecular photosystems, has been slow. Mallouk et al. recently developed electrochemical water-splitting cells using the Ru(II) complex as the visible light photosensitizer. the dye-sensitized PEC cell consisted of a dye-sensitized TiO2 layer, a Pt counter electrode, and an aqueous solution between them. Under a visible light (< 3 eV) illumination, only the dye molecule absorbed the light and became excited because TiO2 had the wide band gap. The light absorption of the dye was followed by the transfer of an electron from the excited state (S*) of the dye to the conduction band (CB) of TiO2 and its subsequent transfer to the transparent conducting oxide (TCO). The electrons moved through the wire to the Pt, where the water reduction (or H2 evolution) occurred. The oxidized dye molecules caused the water oxidation because their HOMO level was below the H2O/O2 level. Organic dyes have been developed as metal-free alternatives to the Ru(II) complexes because of their tunable optical and electronic properties and low-cost manufacturing. Recently, organic dye molecules containing multi-branched, multi-anchoring groups have received a great deal of interest. In this work, tri-branched tri-anchoring organic dyes (Dye 2) were designed and applied to visible light water-splitting cells based on dye-sensitized TiO2 electrodes. Dye 2 had a molecular structure containing one donor (D) and three acceptor (A) groups, and each ended with an anchoring functionality. In comparison, mono-anchoring dyes (Dye 1) were also synthesized. The PEC response of the Dye 2-sensitized TiO2 film was much better than the Dye 1-sensitized or unsensitized TiO2 films.

• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.42-45
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• 2018

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.