• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.59-66
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• 2018

In this paper, we analyzed the usefulness of single-structured printed circuit board (PCB) modeling by using numerical analysis to model the PCB structure applied to a package for semiconductor purposes and applying modeling assuming a single structure. PCBs with circuit layer of 3rd and 4th were used for analysis. In addition, measurements were made on actual products to obtain material characteristics of a single structure PCB. The analysis results showed that if the PCB was modeled in a single structure compared to a multi-layered structure, the warpage analysis results resulting from modeling the PCB structure would increase and there would be a significant difference. In addition, as the circuit layer of the PCB increased, the mechanical properties of the PCB, the elastic coefficient and inertia moment of the PCB increased, decreasing the package's warpage.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.341-344
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• 2000

Several new via structures in printed circuit boards are proposed, fabricated and characterized in RF regime. The new structure with a larger inductance component in the bottom layer shows 3㏈ improvement over the conventional structure. The ADS simulation with model parameters extracted from 3D fie]d solver matches with the characterization of these vias

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.171-173
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• 2002

This paper describes the open frame type high power density switching converter. It is based on active clamp forward converter with synchronous rectifier, and packaged by using the open frame and multi-layer printed circuit board (PCB) techniques to achieve the high power density. Furthermore, windings of transformer and inductor are also realized by multi-layer PCB so that it achieves the higher power density. Through the experiment on the proto-type converter of 50[W], it is confirmed that power density of $50[W/in^3]$ and maximum efficiency of over 91 [%] are obtained.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.11a
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• pp.87-88
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• 2007

• Journal of the Korea Society for Simulation
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• v.1 no.1
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• pp.17-24
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• 1992

The capacity of the drilling process in Multi-Layer PCB fabrication can be affected by various process parameters determining material flows in the unit operations. The ratio of mass-lamination to pin lamination and the number of stacks as the most critical paramaters, among them, were chosen on the basis of exhaustive field evaluation to study their effects on the capacity of the process. The best alternative condition for maximum capacity of the process was selected by simulation of process.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.10
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• pp.14-22
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• 2010

The most costly and time-consuming process in the fabrication of today's multi-layer circuit board is drilling interconnection holes between adjacent layers and via holes within a layer. Decreasing size of via holes being demanded and growing number of via holes per panel increase drilling costs. Component density and electronic functionality of today's multi-layer circuit boards can be improved with the introduction of cost-effective, variable depth laser drilled blind micro via holes, and interconnection holes. Laser technology is being quickly adopted into the circuit board industry but can be accelerated with the introduction of a true production laser drilling system. In order to get optimized condition for drilling to FPCB (Flexible Printed Circuit Board), we use various drill pattern as drill step. For productivity, we investigate drill path optimization method. And for the precise drilling the thermal drift of scanner and temperature change of scan system are tested.

• Journal of Electrical Engineering and Technology
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• v.7 no.4
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• pp.582-588
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• 2012

In this paper, a highly miniaturized and performed UWB bandpass filter has been newly designed and implemented by embedding all the passive elements into a multi-layered PCB substrate with high dielectric $SrTiO_3$ composite film for 3.1 - 4.75 GHz compact UWB system applications. The high dielectric composite film was utilized to increase the capacitance densities and quality factors of capacitors embedded into the PCB. In order to reduce the size of the filter and avoid parasitic EM coupling between the embedded filter circuit elements, it was designed by using a $3^{rd}$ order Chebyshev circuit topology and a capacitive coupled transformation technology. Independent transmission zeros were also applied for improving the attenuation of the filter at the desired stopbands. The measured insertion and return losses in the passband were better than 1.68 and 12 dB, with a minimum value of 0.78 dB. The transmission zeros of the measured response were occurred at 2.2 and 5.15 GHz resulting in excellent suppressions of 31 and 20 dB at WLAN bands of 2.4 and 5.15 GHz, respectively. The size of the fabricated bandpass filter was $2.9{\times}2.8{\times}0.55(H)mm^3$.

• Korean Journal of Materials Research
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• v.18 no.3
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• pp.117-122
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• 2008

Micro-sized bumps on a multi-layered build-up PCB were fabricated by pulse-reverse copper electroplating. The values of the current density and brightener content for the electroplating were optimized for suitable performance with maximum efficiency. The micro-bumps thus electroplated were characterized using a range of analytical tools that included an optical microscope, a scanning electron microscope, an atomic force microscope and a hydraulic bulge tester. The optical microscope and scanning electron microscope analyses results showed that the uniformity of the electroplating was viable in the current density range of $2-4\;A/dm^2$; however, the uniformity was slightly degraded as the current density increased. To study the effect of the brightener concentration, the concentration was varied from zero to 1.2 ml/L. The optimum concentration for micro-bump electroplating was found to be 0.6 ml/L based on an examination of the electroplating properties, including the roughness, yield strength and grain size.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2001.06a
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• pp.3-3
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• 2001

Recently TiN, TiAlN, CrN hardcoatings have adapted many industrial application such as die, mold and cutting tools because of good wear resistant and thermal stability. However, in terms of high speed process, general hard coatings have been limited by oxidation and thermal hardness drop. Especially in the case of PCB drill, high speed cutting and without lubricant process condition have not adapted these coatings until now. Therefore more recently, superhard nanocomposite coating which have superhard and good thermal stability have developed. In previous works, WC-TiAlN new nanocomposite film was investigated by cathodic arc ion plating system. Control of AI concentration, WC-TiAlN multi layer composite coating with controlled microstructure was carried out and provides additional enhancement of mechanical properties as well as oxidation resistance at elevated temperature. It is noted that microhardness ofWC-TiA1N multi layer composite coating increased up to 50 Gpa and got thermal stability about $900^{\circ}C$. In this study WC-TiAlN nanocomposite coating was deposited on PCB drill for enhancement of life time. The parameter was A1 concentration and plasma cleaning time for edge sharpness maintaining. The characteristic of WC-TiAlN film formation and wear behaviors are discussed with data from AlES, XRD, EDS and SEM analysis. Through field test, enhancement of life time for PCB drill was measured.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.