• 전자공학회지
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• 제29권9호
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• pp.18-30
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• 2002

Wireless communication systems will be one of the biggest drivers of semiconductor products over the next decade. Global Positioning System (GPS) and Blue-tooth, HomeRF, and Wireless-LNA system are just a few of RF-module candidate awaiting integration into next generation mobile phone. Motivated by the generation mobile phone. Motivated by the growing needs for low-cost and multi-band/multi-function single chip wireless transceivers, CMOS technology has been recognized as a most promising candidate for the implementation of the future wireless communication systems. This paper presents recent developments in RF CMOS technology, which is classified into device technology and circuit technology and from them forecasts technology and from them forecasts technology trends in the near future.

• 마이크로전자및패키징학회지
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• 제8권2호
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• pp.49-52
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• 2001

This paper presents product level considerations for multichip packaging as a cost effective alternative to single chip packaging in the design and manufacture of mobile telephony products. Important aspects include component functionality and complexity, acquisition and logistics costs, product modularity and integration. Multichip packaging offers unique solutions and significant system level cost savings in many applications including RF modules, digital matrix functions and product options such as security, data storage, voice recognition, etc.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 Proceedings of 6th International Joint Symposium on Microeletronics and Packaging
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• pp.1-7
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• 2001

This paper presents product level considerations for multichip packaging as a cost effective alternative to single chip packaging in the design and manufacture of mobile telephony products. Important aspects include component functionality and complexity, acquisition and logistics costs, product modularity and integration. Multichip packaging offers unique solutions and significant system level cost savings in many applications including RF modules, digital matrix functions and product options such as security, data storage, voice recognition, etc.

• 한국전자파학회논문지
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• 제12권6호
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• pp.906-911
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• 2001

본 논문에서는 비화 통신을 위하여 chirp 방식을 이용한 BPSK 시스템의 LPI(low probability of intercept)와 AJ(anti jamming) 성능을 분석하였다. Chirp 방식은 주파수를 전체 확산대역 내에서 임의적으로 변화시켜 신호의 주기적인 특성을 제거하기 때문에, feature parameter인 chip rate를 검출하는데 용이한 DAM(delay and multiplier)과 반송파 주파수 검출에 용이한 SC(Squaring Circuit)에 대항하여 뛰어난 LPI 특성을 가진다. chirp parameter의 변화에 따른 LPI 특성으로 chirp duration(Tc)이 커질수록 좋은 LPI 성능을 보인다. PBNJ(partial band noise jammer)환경에서, chirp 방식이 이론적인 DSSS(Direct Sequence Spread Spectrum) 방식에 비하여 AJ 성능이 우수함을 시뮬레이션으로 확인하였다. PBNJ와 MTJ(multi-tone jammer)를 비교하였을 때, chirped BPSK 시스템이 동일 JSR(jammer to signal power ratio)에서 MTJ에 더 우수한 AJ 성능이 있다.

• ETRI Journal
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• 제22권4호
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• pp.13-24
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• 2000

As more transistors are integrated onto bigger die, an on-chip multiprocessor will become a promising alternative to the superscalar microprocessor that dominates today's microprocessor marketplace. This paper describes key parts of a new on-chip multiprocessor, called Raptor, which is composed of four 2-way superscalar processor cores and one graphic co-processor. To obtain performance characteristics of Raptor, a program-driven simulator and its programming environment were developed. The simulation results showed that Raptor can exploit thread level parallelism effectively and offer a promising architecture for future on-chip multi-processor designs.

• ETRI Journal
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• 제36권2호
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• pp.293-300
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• 2014

As the system-on-chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.

• 한국통신학회논문지
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• 제26권12B호
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• pp.1637-1647
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• 2001

Multi-Code CDMA (MC-CDMA) 방식은 송신 시 여러 채널의 신호를 동시에 선형적으로 합하여 전송하므로 채널수가 증가할수록 신호의 PAPR(Peak to Average Power Ratio)가 증가하게 되어 증폭기의 비선형 특성에 의해 시스템 성능이 변화한다. 본 논문에서는 다중 레벨 신호에 대한 증폭기의 비선형 왜곡 특성을 분석하고, 증폭기의 비선형 특성에 의한 영향을 최소화하기 위해 다중 레벨 신호를 constant envelope 신호로 변환하는 Multi-Phase CDMA (MP-CDMA) 방식을 제안한다. 또한 다중 레벨 신호의 일정 레벨 이상은 잘라버리는 clipping 방식을 적용함으로써 레벨수의 증가에 따른 성능 저하 및 시스템의 복잡화를 줄이며 이로 인한 시스템 성능의 변화와 요구 전송 속도에 따른 최적의 clipping level을 연구한다.

• 로봇학회논문지
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• 제4권1호
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• pp.1-9
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• 2009

Radio Frequency Identification (RFID) is an automatic identification method. Information such as identification, logistics history, and specification of products are written and stored into the memory of RFID tags (that is, transponders), and retrieved through RF communication between RFID reader device and RFID tags. RFID systems have been applied to many fields of transportation, industry, logistics, environment, etc in order to improve business efficiency and reduce maintenance cost as well. Recently, some research results are announced in which RFID devices are combined with other sensors for mobile robot localization. In this paper, design of multi-protocol baseband for RFID reader device is proposed, and the baseband modem is implemented into SoC (System On a Chip). The baseband modem SoC for multi-protocol RFID reader is composed of several IP (Intellectual Property) blocks such as multi-protocol blocks, CPU, UART(Universal Asynchronous Receiver and Transmitter), memory, etc. As a result, the SoC implemented with FPGA(Field Programmable Gate Array) is applied to real product. It is shown that the size of RFID Reader module designed with the FPGA becomes smaller, and the SoC chip price for the same function becomes cheap. In addition, operation performance could be the same or better than that of the product with no SoC applied.

• 대한의용생체공학회:의공학회지
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• 제22권3호
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• pp.285-291
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• 2001

In this paper, we designed two preprocessing adaptive filter - high pass filter and notch filter - using FPGA. For minimizing the calculation load of multi-channel and high-resolution ECG system, we utilize FPGA rather than digital signal processing chip. To implement the designed filters in FPGA, we utilize FPGA design tool(Altera corporation, MAX-PLUS II) and CSE database as test data. In order to evaluate the performance in terms of processing time, we compared the designed filters with the digital filters implemented by ADSP21061(Analog Devices). As a result, the filters implemented by FPGA showed better performance than the filters based on ADSP21061. As a consequence of examination, we conclude that FPGA is a useful solution in multi-channel and high-resolution signal processing.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2006년도 춘계학술대회 논문집
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• pp.154-156
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• 2006

A few ten mW white LED can substitute for the indicator light source and it is required to study several watt multi-chip semiconductor light sources in order to replace the light sources for general illumination such as incandescent lights and fluorescent lanes. Since the optical technology used for several mW white LED light source uses only 30% to 52% of the light it is required to develop the design technology of optical system and lens to improve the efficiency more than 80% for insuring the high power of white LED. In this paper, we designed and fabricated new structure reflector to increase the efficiency and is easy to make high power multi-chip LED lamp.