• 전기학회논문지
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• 제56권8호
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• pp.1424-1429
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• 2007

This paper presents a simple and reliable one-touch type multi-immunosensing lab-on-a-chip (LOC) detecting antibodies as multi-disease markers using electrochemical method suitable for a portable point-of-care system (POCS). The multi-stacked LOC consists of a PDMS space layer for liquids loading, a PDMS valve layer with 50 im in height for the membrane, a PDMS channel layer for the fluid paths, and a glass layer for multi electrodes. For the disposable immunoassay which needs sequential flow control of sample and buffer liquids according to the designed strategies, reliable and easy-controlled on-chip operation mechanisms without any electric power are necessary. The driving forces of sequential liquids transfer are the capillary attraction force and the pneumatic pressure generated by air bladder push. These passive fluid transport mechanisms are suitable for single-use LOC module. Prior to the application of detection of the antibody as a disease marker, the model experiments were performed with anti-DNP antibody and anti-biotin antibody as target analytes. The flow test results demonstrate that we can control the fluid flow easily by using the capillary stop valve and the PDMS check valves. By the model tests, we confirmed that the proposed LOC is easily applicable to the bioanalytic immunosensors using bioelectrocatalysis.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• 전기학회논문지
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• 제58권1호
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• pp.147-154
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• 2009

This paper presents a grating~integrated SPR (Surface Plasmon Resonance) sensor chip for simple and inexpensive biomolecule detection. The grating-integrated SPR sensor chip has two sensing channels having a nano grating for SPR coupling. An external mirror is used for multi channel SPR sensing. The present sensor chip replaces bulky and expensive optical components, such as fiber-optic switches or special shaped prisms, resulting in a simple and inexpensive wavelength modulated multi-channel SPR sensing system. We fabricate a SPR sensor chip integrated with 835 nm-pitch gratings by a micromolding technique to reduce the fabrication cost. In the experimental characterization, the refractive index sensitivity of each sensing channel is measured as $321.8{\pm}8.1nm$/RI and $514.3{\pm}8.lnm$/RI, respectively. 0.5uM of the target biomolecule (streptavidin) was detected by a $1.13{\pm}0.16nm$ shift of the SPR dip in the 10%-biotinylated sample channel, while the SPR dip in the reference channel for environmental perturbation monitoring remained at the same position. From the experimental results, multi-channel biomolecule detection capability of the present grating-integrated SPR sensor chip has been verified. On the basis of the preliminary experiments, we successfully measured the binding reaction rate for the $2\;nM{\sim}200\;nM$ monoclonal-antibiotin, thus verifying biomolecule concentration detectability of the present SPR sensor chip. The binding reaction rates measured from the present SPR sensor chip agredd well with those from a commercialized SPR sensor.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.925-928
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• 1999

A multi-channel gas leakage monitoring system was designed and fabricated by using CPLD(complex Programmable Logic .Device) for monitoring and controlling the leakage of natural gas from supplying-pipes under the ground. Fabricated SnO$_2$thick film gas sensor elements were attached on safeguard steel plate of natural gas supplying pipes, and the local monitoring system in this study received the signal from the gas sensors. The monitoring system was implemented by using CPLD chip to reduce the development time and implement simple one chip system. The time division multi-channel system received the input signal from individual gas sensor at one of divided times by multiplexor and signal processed sequentially. The system reduced the size of peripheral circuit resulted in implementation of creditable simple system.

• IEIE Transactions on Smart Processing and Computing
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• 제5권1호
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• pp.55-62
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• 2016

In this paper, we propose a hybrid multi.system-on-chip (H-MSoC) architecture that provides a high-flexibility system in a rapid development time. The H-MSoC approach provides a flexible system-on-chip (SoC) architecture that is easy to configure for physical- and application-layer development. The physical- and application-layer aspects are dynamically designed and modified; hence, it is important to consider a design methodology that supports rapid SoC development. Physical layer development refers to intellectual property cores or other modular hardware (HW) development, while application layer development refers to user interface or application software (SW) development. H-MSoC is built from multi-SoC architectures in which each SoC is localized and specified based on its development focus, either physical or application (hybrid). Physical HW development SoC is referred to as physical-SoC (Phy-SoC) and application SW development SoC is referred to as application-SoC (App-SoC). Phy-SoC and App-SoC are connected to each other via Ethernet. Ethernet was chosen because of its flexibility, high speed, and easy configuration. For prototyping, we used a LEON3 SoC as the Phy-SoC and a ZYNQ-7000 SoC as the App-SoC. The proposed design was proven in real-time tests and achieved good performance.

• 한국통신학회논문지
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• 제22권7호
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• pp.1590-1598
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• 1997

The paper first introduces the new concept of potential diversity and signal decomposability, which establish a foundaton to generalize the existing concepts of path and frequency diversities. Then it presents a new DS/CDMA system called chip-spreading OCDM system, which is an embodiment of the petential diversity concept that combines the path diversity of the DS/CDMA system and the frequency diversity of the OFDM/CDMA system. In the chip-spreading OCDM system the chip sequences in each symbol interval are first converted into aralled streams, which then simultaneously modulate different orthogonal Walsh basis functions. In the receiver, the received signal is matched to each extended basis-function which is the union of the transmitter basis-functions and their delayed replicas, and the matched-filtered chip samples are combined together after individual channel compensation. The conventional DS/CDMA system using the maximal ratio combining. In addition, it effectively resolves the high PAR and high sensitivity to frequency offset problems which are critical in multi-carrier systems.

• 한국전자파학회논문지
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• 제25권5호
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• pp.504-514
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• 2014

본 논문에서는 X-대역 능동 위상 배열 레이더 시스템에 사용되는 MMIC 다기능 칩을 0.5 ${\mu}m$ p-HEMT 상용 공정을 이용하여 저전력 특성을 가지도록 개발하였다. 다기능 칩은 6-비트 디지털 위상 천이 기능, 6-비트 디지털 감쇠 기능, 송/수신 모드 선택 기능, 신호 증폭 기능 등의 다양한 기능을 제공한다. $16mm^2(4mm{\times}4mm)$ 칩 크기의 소형으로 제작된 MMIC 다기능 칩은 7~11 GHz에서 10 dB의 송/수신 이득 특성과 14 dBm의 P1dB 특성을 가지며, DC 소모 전력이 0.6 W로 매우 낮은 저전력 특성을 보였다. 그리고 6-비트, 64 상태에 대해 위상 천이 특성과 감쇠 특성의 측정 결과, 동작 주파수에서 $3^{\circ}$의 RMS(Root Mean Square) 위상 오차와 0.6 dB의 RMS 감쇠 오차를 보였다.

• 대한기계학회논문집A
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• 제30권4호
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• pp.373-378
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• 2006

We present the design, fabrication, and characterization of a multi-chip microelectrofluidic bench, achieving both electrical and fluidic interconnections with a simple, low-loss and low-temperature electrofluidic interconnection method. We design 4-chip microelectrofluidic bench, having three electrical pads and two fluidic I/O ports. Each device chip, having three electrical interconnections and a pair of two fluidic I/O interconnections, can be assembled to the microelectofluidic bench with electrical and fluidic interconnections. In the fluidic and electrical characterization, we measure the average pressure drop of $13.6{\sim}125.4$ Pa/mm with the nonlinearity of 3.1 % for the flow-rates of $10{\sim}100{\mu}l/min$ in the fluidic line. The pressure drop per fluidic interconnection is measured as 0.19kPa. Experimentally, there are no significant differences in pressure drops between straight channels and elbow channels. The measured average electrical resistance is $0.26{\Omega}/mm$ in the electrical line. The electrical resistance per each electrical interconnection is measured as $0.64{\Omega}$. Mechanically, the maximum pressure, where the microelectrofluidic bench endures, reaches up to $115{\pm}11kPa$.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2011년 춘계학술대회논문집
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• pp.117-123
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• 2011

The low electric power and high efficiency chips are required because of the appearance of smart phones. Also, high-capacity memory chips are needed. e-MMC(embedded Multi-Media Card) for this is defined by JEDEC(Joint Electron Device Engineering Council). The e-MMC memory for research and development is a memory mulit-chip module of 64GB using 16-multilayers of 4GB NAND-flash memory. And it has simplified the chip by using SIP technique. But mulit-chip module generates high heat by higher integration. According to the result of study, whenever semiconductor chip is about 10 $^{\circ}C$ higher than the design temperature it makes the life of the chip shorten more than 50%. Therefore, it is required that we solve the problem of heating value and make the efficiency of e-MMC improved. In this study, geometry of 16-multilayered structure is compared the temperature distribution of four different geometries along the numerical analysis. As a result, it is con finned that a multilayer structure of stair type is more efficient than a multilayer structure of vertical type because a multi-layer structure of stair type is about 9 $^{\circ}C$ lower than a multilayer structure of vertical type.

• ETRI Journal
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• 제27권5호
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• pp.497-503
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• 2005

In this paper, we present a performance analysis for an MPEG-4 video codec based on the on-chip network communication architecture. The existing on-chip buses of system-on-a-chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on-chip network is introduced to solve the problem of on-chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG-4 video codec based on the on-chip network and Advanced Micro-controller Bus Architecture (AMBA) on-chip bus. Experimental results show that the performance of the MPEG-4 video codec based on the on-chip network is improved over 50% compared to the design based on a multi-layer AMBA bus.