• 한국시뮬레이션학회논문지
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• 제26권1호
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• pp.69-75
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• 2017

MCP(Multi-chip Package)는 두 개 이상의 Chip을 적층하여 하나의 패키지로 합친 제품이다. MCP를 만들기 위해서는 두 개 이상의 Chip이 동일한 Substrate에 적층되기 때문에 다수의 조립 공정이 필요하다. Package 공정에서는 Lot들이 동일한 특성을 가지는 Chip으로 구성되고 MCP를 구성하는 Chip의 특성은 Layer sequence에 의해 결정된다. MCP 생산 공정에서 WIP Balance 뿐만 아니라 Throughput을 달성하기 위해서는 Chip의 Layer sequence가 중요하다. 본 논문에서는 Chip들의 Layer sequence의 제약 조건을 고려한 스케쥴링 방법론을 제안한다.

• 반도체디스플레이기술학회지
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• 제6권1호
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• pp.17-22
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• 2007

Recent new packages such as MCP(Multi-Chip Package), QDP(Quadratic Die Package) and DDP(Dual Die Package) have stack type configuration. This kind of multi-layer package is thicker than single layer package. So there is need for the low height looping technology in wirebonder to make these packages thinner. There is stiff zone above ball in wirebonder wire which is called HAZ(Heat Affect Zone). When making low height loop (below $80\;{\mu}m$) with traditional forward loop, stiff wire in HAZ(Heat Affected Zone) above ball is bended and weakened. So the traditional forward looping method cannot be applied to low height loop. SSB(stand-off stitch) wire bonding method was applied to many packages which require very low loops. The drawback of SSB method is making frequent errors at making ball, neck damage above ball on lead and the weakness of ball bonding on lead. The alternative looping method is BNL(ball neckless) looping technology which is already applied to some package(DDP, QDP). The advantage of this method is faster in bonding process and making little errors in wire bonding compared with SSB method. This paper presents the result of BNL looping technology applied in assembly house and several issues related to low loop height consistence and BNL zone weakness.

• 비파괴검사학회지
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• 제35권3호
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• pp.200-205
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• 2015

현대의 컴팩트 반도체 소자들은 정확한 품질검사를 위해 비파괴, 고분해능의 검사 장비가 요구되고 있다. 검사 장비 중 고분해능 적외선 대물렌즈와 적외선 센서로 구성된 초정밀 열영상 현미경은 반도체 내부의 결함에서 발생되는 국소적 열원의 위치와 깊이 정보를 얻는데 유용하게 활용되고 있다. 본 연구에서는 위 상잠금기법이 적용된 적외선열영상 현미경을 이용하여 다층구조로 된 반도체 소자 내부 열원의 위치와 깊이 정보에 대해 분석하였다. 시편은 내부에 3개의 열원을 포함한 TSV(through silicon via technology) 기반 4단 적층구조로서 측정 표면으로부터 열원의 깊이는 $240{\mu}m$이다. 본 실험에서는 위상잠금기법을 통해 시편 내부열원의 위치와 깊이를 정확히 찾을 수 있는 초점면 위치, 노출시간 그리고 위상잠금주파수 등 최적의 조건을 찾고 그 조건에서 적외선 대물렌즈와 시편의 거리 변화에 따른 위상 변이와 깊이 정보에 대한 영향을 알아보았다. 이와 같은 반도체 내부결함에 의한 열원의 위치와 깊이 분석에 대한 연구는 품질검사용 열영상 분석장비 개발에 큰 도움을 줄 것으로 예상한다.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2011년 춘계학술대회논문집
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• pp.117-123
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• 2011

The low electric power and high efficiency chips are required because of the appearance of smart phones. Also, high-capacity memory chips are needed. e-MMC(embedded Multi-Media Card) for this is defined by JEDEC(Joint Electron Device Engineering Council). The e-MMC memory for research and development is a memory mulit-chip module of 64GB using 16-multilayers of 4GB NAND-flash memory. And it has simplified the chip by using SIP technique. But mulit-chip module generates high heat by higher integration. According to the result of study, whenever semiconductor chip is about 10 $^{\circ}C$ higher than the design temperature it makes the life of the chip shorten more than 50%. Therefore, it is required that we solve the problem of heating value and make the efficiency of e-MMC improved. In this study, geometry of 16-multilayered structure is compared the temperature distribution of four different geometries along the numerical analysis. As a result, it is con finned that a multilayer structure of stair type is more efficient than a multilayer structure of vertical type because a multi-layer structure of stair type is about 9 $^{\circ}C$ lower than a multilayer structure of vertical type.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.531-531
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• 2012

So many groups have been researching the green quantum dots such as InP, InP/ZnS for overcoming the semiconductor nanoparticles composed with heavy metals like as Cd and Pb so on. In spite of much effort to keep up CdSe quantum dots, it does not reach the good properties compared with CdSe/ZnS quantum dots. This quantum dot has improved its properties through the generation of core/shell CdSe/ZnS structure or core/multi-shell structures like as CdSe/CdS/ZnS and CdSe/CdS/ CdZnS/ZnS. In this research, we try to synthesize the InP multi-shell structure by the successiveion layer absorption reaction (SILAR) in the one pot. The synthesized multi-shell structure has improved quantum yield and photo-stability. To generate white light, highly luminescent InP multi-shell quantum dots were mixed with yellow phosphor and integrated on the blue LED chip. This InP multi-shell improved red region of the LEDs and generated high CRI.

• 비파괴검사학회지
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• 제20권6호
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• pp.511-520
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• 2000

초음파 펄스-에코법을 매우 얇은 층을 갖는 다층구조물에 적용할 때 그 얇은 층의 상하면에서의 반사파가 중첩되게 되면 검사가 곤란하게 된다. 이런 문제는 반도체 내부에서의 심한 감쇠를 피하기 위해 20MHz 이하의 비교적 저주파수를 사용하는 초음파 현미경으로 반도체의 얇은 실리콘 칩을 검사하는 경우에 쉽게 볼 수 있다. 기존에 이런 초음파 신호의 중첩을 분리하기 위해 디컨볼루션 기법이 사용되어 왔으나, 송신파의 파형이 전파하면서 왜곡되어 수신되는 경우에는 적절치 못하다. 본 논문에서는 기존의 디컨볼루션 기법에 비하여 우수한 성능으로 중첩 신호를 분리해 낼 수 있는 새로운 신호처리 기법으로서 웨이브렛 변환 기반 디컨볼루션 (WTBD) 기법을 제안하였다. 여기서 웨이브렛 변환은 송신파와 왜곡된 수신 신호의 공통 파형을 추출하기 위해 사용되고 추출된 공통 파형에 대해 디컨볼루션 처리한다. 제안하는 방법의 성능은 모형신호에 대한 컴퓨터 시뮬레이션과 인위적으로 실리콘 칩 상면에 들뜸 결함을 만든 반도체 시편에 대한 실험을 통해 검증되었다.

• 한국정밀공학회지
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• 제22권2호
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• pp.38-45
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• 2005

Chemical mechanical polishing(CMP) has been widely accepted for the planarization of multi-layer structures in semiconductor fabrication. But a variety of defects such as abrasive contamination, scratch, dishing, erosion and corrosion are occurred during CMP. Especially, dishing and erosion defects increase the metal resistance because they decrease the interconnect section area, and ultimately reduce the lift time of the semiconductor. Due to this reason dishing and erosion must be prohibited. The pattern density and size in chip have a significant influence on dishing and erosion occurred by over-polishing. The fixed abrasive pad(FAP) was applied and tested to reduce dishing and erosion in this paper. The abrasive concentration decrease of FAP results in advanced pattern selectivity which can lead the uniform removal in chip and declining over-polishing. Consequently, reduced dishing and erosion was observed in CMP of tungsten pattern wafer with proposed FAP and chemicals.

• 세라미스트
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• 제21권2호
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• pp.4-18
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• 2018

Lastly, neuromorphic computing chip has been extensively studied as the technology that directly mimics efficient calculation algorithm of human brain, enabling a next-generation intelligent hardware system with high speed and low power consumption. Three-terminal based synaptic transistor has relatively low integration density compared to the two-terminal type memristor, while its power consumption can be realized as being so low and its spike plasticity from synapse can be reliably implemented. Also, the strong electrical interaction between two or more synaptic spikes offers the advantage of more precise control of synaptic weights. In this review paper, the results of synaptic transistor mimicking synaptic behavior of the brain are classified according to the channel material, in order of silicon, organic semiconductor, oxide semiconductor, 1D CNT(carbon nanotube) and 2D van der Waals atomic layer present. At the same time, key technologies related to dielectrics and electrolytes introduced to express hysteresis and plasticity are discussed. In addition, we compared the essential electrical characteristics (EPSC, IPSC, PPF, STM, LTM, and STDP) required to implement synaptic transistors in common and the power consumption required for unit synapse operation. Generally, synaptic devices should be integrated with other peripheral circuits such as neurons. Demonstration of this neuromorphic system level needs the linearity of synapse resistance change, the symmetry between potentiation and depression, and multi-level resistance states. Finally, in order to be used as a practical neuromorphic applications, the long-term stability and reliability of the synapse device have to be essentially secured through the retention and the endurance cycling test related to the long-term memory characteristics.

• 반도체디스플레이기술학회지
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• 제17권4호
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• pp.42-45
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• 2018

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.