• Journal of KIISE:Software and Applications
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• v.34 no.5
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• pp.487-501
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• 2007

To achieve high resource utilization for multi-issue DSPs, production compiler commonly includes variants of iterative modulo scheduling algorithm. However, excessive cyclic data dependences, which exist in communication and media processing loops, unduly restrict modulo scheduling freedom. As a result, replicated functional units in multi-issue DSPs are often under-utilized. To address this resource under-utilization problem, our paper describes a novel compiler preprocessing strategy for effective modulo scheduling. The preprocessing strategy proposed capitalizes on two new transformations, which are referred to as cloning and dismantling. Our preprocessing strategy has been validated by an implementation for StarCore SC140 DSP compiler.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.4
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• pp.85-92
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• 2019

This paper presents a SDR-based Long Term Evolution Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a multicore Digital Signal Processor (DSP). For decoder implementation, multicore DSP TMS320C6670 is used, which provides various hardware accelerators such as turbo decoder, fast Fourier transformer and Bit Rate Coprocessors. The TMS320C6670 is a DSP specialized in implementing base station platforms and is not an optimized platform for implementing mobile terminal platform. Accordingly, in this paper, the hardware accelerator was changed to the terminal implementation to implement the LTE-A PDSCH decoder supporting the multi-antenna and the functions not provided by the hardware accelerator were implemented through core programming. Also pipeline using multicore was implemented to meet the transmission time interval. To confirm the feasibility of the proposed implementation, we verified the real-time decoding capability of the PDSCH decoder implemented using the LTE-A Reference Measurement Channel (RMC) waveform about transmission mode 2 and 3.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.3
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• pp.185-190
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• 2022

We propose a high speed data communication method for motor drive systems with fast control cycle in order to collect state variables of motor control without degrading control performance. Ethernet is chosen for communication device, and multi-core DSP architecture is exploited for communication processing load distribution. The communication program including network protocol stack and motor control program are assigned to two separate cores, and data between two cores are exchanged using interrupt-based inter-process communication mechanism, which enables to achieve a high-speed communication performance without degrading the motor control performance. The performance of developed communication method is demonstrated by real experiments using TCP, UDP and Raw Socket protocols in an experimental setup consisting of TI's TMS320F28388D motor control card and MS Windows PC.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.199-203
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• 1999

This paper is on the DSP system design and implementation for real time MPEG-2 AAC multichannel audio, and MPEG-4 object oriented audio coding. This DSP system employs two DSPs of the state of the art TMS320C6701, developed by TI semiconductor. DSP board has PCI interface for downloading application program and control the system. DSP board was designed to use for both encoder and decoder, by setting several switches. The system contains external input and output box also, for A/D and D/A conversion for eight channel audio. The input box converts multi channel digital audio to ADI format, that provides serial interface for eight channel digital audio. And the output box converts ADI format signal to multi channel audio. Through this ADI interface, DSP boards can be connected to input, output box. Implemented DSP system was tested for integration with MPEG-2 AAC encoder and decoder S/W. Currently the DSP system performs realtime AAC 4-channel audio encoding with two DSPs, and 8-channel decoding with one DSP.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.12
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• pp.609-614
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• 2001

This paper presents a multi output converter system that controls, simultaneously and independently, the separate Buck converter and Boost converter with the different specification by one DSP digital controller. As two separate converters are regulated by only one DSP, it is possible to achieve the simple digital control circuit for regulating multi output DC-DC converter. By setting the software switch state, PI and Fuzzy controller can be applied as a controller for each converter without any change of hardware. Also, it is included the control characteristics comparison between PI and Fuzzy controller. The control characteristics of each PWM DC-DC converter is validated by experimental results.

• Journal of Power Electronics
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• v.9 no.3
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• pp.410-417
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• 2009

This paper represents a design and implementation of a digital controller for a multi-phase synchronous buck converter (SBC) using a digital signal processor (DSP). The multi-phase SBC has generally been used for a voltage regulation module (VRM) of a microprocessor because of its high current handling capability at a low output voltage. The VRM requires high control performance of tight output regulation, high slew rate, and load sharing capability of multiple converters. In order to achieve these requirements, the design and implementation of a digital control system for a multi-phase SBC are presented in this paper. The digital PWM generation, current sensing, and voltage and current controller using a DSP TMS320F2812 are considered. The experimental results are provided to show the validity of the implemented digital control system.

• The Journal of the Acoustical Society of Korea
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• v.16 no.3E
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• pp.56-61
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• 1997

In this paper, we describe a real-time implementation of a multi-channel auido codec system that is based on the MPEG-1 audio algorithm. The major feature of this system is that it has a flexible multi-DSP system that can be adapted for various applications with using up to four TMS320C40 DSPs. The purpose of this paper is to present the problems of the system and is to describe the optimized methods to solve the problems in the view of hardware and software. Our audio codec is composed of an encoder an a decoder system and the bit rate of bitstream is up to 384 kbps. Fast input/output interfaces, DSP overloads, and inter-DSP communications methods with high speed are considered in multi-DSP H/W. Also, to run real-time in S/W, optimizing methods of algorithm are considered. After implementation of system, the subjective assessment method, and 'triple stimulus/hidden reference/double blind' that recommended by ITU-R TG10/3 is adopted for the quality of our system. All test items except one are awarded difference grades(diffgrade) better than 1-. Form the results, multi-channel audio system can be used for HDTV service.

• Journal of Biomedical Engineering Research
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• v.20 no.4
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• pp.495-502
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• 1999

We propose efficient speech signal processing algorithms and a system for cochlear implant in this paper. The outer and the middle car which perform amplifying, lowpass filtering and AGC, are modeled by an analog system, and the inner ear acting as a time-delayed multi filter and the transducer is implemented by the DSP circuit which enables real-time processing. Especially, the basilar membrane characteristic of the inner ear is modeled by a nonlinear filter bank, and then tonotopy and periodicity of the auditory system is satisfied by using a pitch-synchronous multi-spectra(PSMS) method. Moreover, most of the speech processing is performed by S/W so the system can be easily modified. And as our program is written in C-language, it can be easily transplanted to the system using other processors.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1
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• pp.56-61
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• 2001

This paper presents the real-time implementation of an AMR (Adaptive Multi Rate) vocoder which is included in the asynchronous International Mobile Telecommunication (IMT)-2000 mobile ASIC. The implemented AMR vocoder is a multi-rate coder with 8 modes operating at bit rates from 12.2kbps down to 4.75kbps. Not only the encoder and the decoder as basic functions of the vocoder are implemented, but VAD (Voice Activity Detection), SCR (Source Controlled Rate) operation and frame structuring blocks for the system interface are also implemented in this vocoder. The DSP for AMR vocoder implementation is a 16bit fixed-point DSP which is based on the TeakLite core and consists of memory block, serial interface block, register files for the parallel interface with CPU, and interrupt control logic. Through the implementation, we reduce the maximum operating complexity to 24MIPS by efficiently managing the memory structure. The AMR vocoder is verified throughout all the test vectors provided by 3GPP, and stable operation in the real-time testing board is also proved.

• The Journal of the Acoustical Society of Korea
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• v.21 no.7
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• pp.648-655
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• 2002

This paper describes implementation of a multi-channel G.723.1 Annex A (G.723.1A) focused on code optimization using a high performance general purpose Digital Signal Processor (DSP), To implement a multi-channel G.723.1A functional complexities of the ITU-T G.723.1A fixed-point C-code are measures an analyzed. Then we sort and optimize C functions in complexity order. In parallel with optimization, we verify the bit-exactness of the optimized code using the ITU-T test vectors. Using only internal memory, the optimized code can perform full-duplex 17 channel processing. In addition, we further increase the number of available channels per DSP into 22 using fast codebook search algorithms, referred to as bit -compatible optimization.