• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1383-1386
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• 2003

In this paper, an ALU for Simultaneous Multi-Threading (SMT) microprocessors is designed. The SMT architecture improves notably performance and utilization of processes compared with conventional superscalar architectures by executing instructions from multiple threads at the same time. This ALU adopts data bypassing method to process multi-threads. And it can flush instructions in the same thread that generate exceptions such as branch misprediction. interrupt etc, performance of SMT microprocessors with data bypassing and exception handler can be improved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.347-357
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• 2004

Network systems have been developed to meet the high performance of forwarding packets and flexibility for providing various services, so network processor emerged. In order to improve the performance of network processors, fast external interface and special functional units have been used. Recently as an architectural method of improving performance, the SMT(Simultaneous Multi Threading) architecture is proposed, but this architecture is difficult to implement due to its complexity. Therefore research for architectural optimization is needed to develop the SMT network processors. In this paper we analyze each functional units on performing network algorithms and propose an optimized SMT network Processor architecture.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.9 s.174
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• pp.107-114
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• 2005

With the recent progress in flexible manufacturing systems (FMS) in industry, increasing attention has been given to Automatic Guided Vehicle (AGV) systems. An AGV is a self-powered unit for transporting materials between stations without needing to be controlled by an operator. Such a system has several sensors to recognize the external state, and it is designed to travel between stations automatically without external assistance. To manage each device automatically in real time it requires a distributed controller with a main computer as the host, as well as a number of micro-controllers. In this study, an AGV system with dual motor drive was constructed. A Pentium 4 personal computer was set up as the main host for the distributed control, and this communicated with other micro-controllers in the management of the motor. The speed of each motor was also controlled by a micro-controller.

• Journal of Digital Convergence
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• v.12 no.6
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• pp.349-354
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• 2014

A maze-escaping method with cooperating work of robots alongside one another will be proposed in this paper. Educational robots can communicate each other using Zigbee; however, they can't solve problems together due to their lack of arithmetic function. The robots walk upright controlled by a motion program; furthermore, they recognize an intersection or a dead-end in the use of distant sensors with sending data and receiving commands from the central control system. The maze-search algorithms were modified so that all robots can effectively navigate the maze.

• The KIPS Transactions:PartA
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• v.18A no.1
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• pp.19-24
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• 2011

As era of multi-core processors has arrived, transactional memory has been considered as an effective method to achieve easy and fast multi-threaded programming. Various hardware transactional memory systems such as UTM, VTM, FastTM, LogTM, and LogTM-SE, have been introduced in order to implement high-performance multi-core processors. Especially, LogTM-SE has provided study performance with an efficient memory management policy and a practical thread scheduling method through conflict detection based on signatures. However, increasing number of cores on a processor imposes the hardware complexity for signature processing. This causes overall performance degradation due to the heavy workload on signature comparison. In this paper, we propose a new architecture of multiple signature comparison to improve conflict detection of signature based transactional memory systems.

• Journal of Broadcast Engineering
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• v.23 no.5
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• pp.682-692
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• 2018

In this paper, we propose an ARQ packet error control scheme using multiple threads in delivering massive capacity of multimedia based on MMT(MPEG Media Transport) protocol. On the sending side, each frame that constitutes an image is packetized into MMT packets based on MMT protocol. The header of the packet stores the sequence number of the frames contained in the packet and the time of presentation information. The payload of the packet stores the direct information that comprises the frame. The generated MMT packet is transmitted to the IP network. The receiving side checks if any error has occurred in the received packet. For any identified error, it controls the error through ARQ error control scheme and reconfigure the frame according to the information stored in the header of the received packet. At this point, a multi-threading based transport design is constructed so that each thread takes over a single frame, which increases the transmission efficiency of massive capacity multimedia. The efficiency of the multi-threading transport method is verified by solving the problems that might arise when using a single-thread approach if packets with errors are retransmitted.

• Journal of Institute of Control, Robotics and Systems
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• v.16 no.1
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• pp.90-95
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• 2010

This paper describes the development of integrated head and eye tracker system. Vision based head tracker is performed and it has 7mm error in 300mm translation. The epi-polar method and point matching are used for determining a position of head and rotational degree. High brightness LEDs are installed on helmet and the installed pattern is very important to match the points of stereo system. Eye tracker also uses LED for constant illumination. A Position of gazed object(3m distance) is determined by pupil tracking and eye tracker has 1~5 pixel error. Integration of result data of each tracking system is important. RS-232C communication is applied to integrated system and triggering signal is used for synchronization.

• Proceedings of the Korean Society of Computer Information Conference
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• 2012.07a
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• pp.297-300
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• 2012

현재 cache의 성능 향상을 위한 많은 기법들이 제안되고 있으며, Latency Hiding 기법 역시 cache의 효율적인 사용을 위해 많은 연구가 진행 되어 왔다. write buffer를 사용한 write Latency hiding기법이나 multi threading을 사용한 Latency Hiding 방법 등 여러 기법들이 연구되어 왔으며, 지금도 Latency hiding을 위한 많은 연구들이 지속적으로 진행되고 있다. 본 논문 역시 효율적인 Latency Hiding을 위한 누적 버퍼를 제안한다. 본 논문은 누적 버퍼의 활용도를 조사하여 얼마나 효율적으로 Latency를 은폐했는지, 또 버퍼를 사용함으로써 얻는 다른 이점에 대해 집중적으로 연구하였다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.72-79
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• 2011

The importance of parallel programming seriously emerges ever since the modern microprocessor architecture has been shifted to the multi-core system. Transactional Memory has been proposed to address synchronization which is usually implemented by using locks. However, the lock based synchronization method reduces the parallelism and has the possibility of causing deadlock. In this paper, we propose an efficient method to utilize transactional memory for the situation which has high contention. The proposed idea is based on the theoretical analysis and it is verified with simulation results. The simulation environment has been implemented using HTM(Hardware Transactional Memory) systems. We also propose a model of the dining philosopher problem to discuss the efficient resource management using the transactional memory technique.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.35 no.3
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• pp.187-194
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• 2017

The present study introduces a method to parallelize k-means clustering algorithm for fast unsupervised classification of large satellite imagery. Known as a representative algorithm for unsupervised classification, k-means clustering is usually applied to a preprocessing step before supervised classification, but can show the evident advantages of parallel processing due to its high computational intensity and less human intervention. Parallel processing codes are developed by using multi-threading based on OpenMP. In experiments, a PC of 8 multi-core integrated CPU is involved. A 7 band and 30m resolution image from LANDSAT 8 OLI and a 8 band and 10m resolution image from Sentinel-2A are tested. Parallel processing has shown 6 time faster speed than sequential processing when using 10 classes. To check the consistency of parallel and sequential processing, centers, numbers of classified pixels of classes, classified images are mutually compared, resulting in the same results. The present study is meaningful because it has proved that performance of large satellite processing can be significantly improved by using parallel processing. And it is also revealed that it easy to implement parallel processing by using multi-threading based on OpenMP but it should be carefully designed to control the occurrence of false sharing.