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An Optimal SMT Processor Architecture for IPv4 Packet Routing  

임정빈 (연세대학교 전기전자공학과)
홍인표 (연세대학교 전기전자공학과)
조정현 (연세대학교 전기전자공학과)
이용석 (연세대학교 전기전자공학과)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.29, no.3A, 2004 , pp. 347-357 More about this Journal
Abstract
Network systems have been developed to meet the high performance of forwarding packets and flexibility for providing various services, so network processor emerged. In order to improve the performance of network processors, fast external interface and special functional units have been used. Recently as an architectural method of improving performance, the SMT(Simultaneous Multi Threading) architecture is proposed, but this architecture is difficult to implement due to its complexity. Therefore research for architectural optimization is needed to develop the SMT network processors. In this paper we analyze each functional units on performing network algorithms and propose an optimized SMT network Processor architecture.
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