• Title/Summary/Keyword: Modulation Index (MI)

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Maximum Modulation Index of VSC HVDC based on MMC Considering Compensation Signals and AC Network Conditions (전력계통 전압 변동과 순환 전류 보상 성분을 고려한 MMC 기반 VSC-HVDC의 최대 변조 지수 선정에 관한 연구)

  • Kim, Chan-Ki;Belayneh, Negesse Belete;Park, Chang-Hwan;Kim, Jang-Mok
    • The Transactions of the Korean Institute of Power Electronics
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    • v.25 no.1
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    • pp.61-67
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    • 2020
  • This study deals with the modulation index (MI) of a voltage source converter (VSC) HVDC system based on a modular multilevel converter (MMC). In the two-level converter, the purpose of the MI is to maximize the achievable AC voltage of the converter from a fixed DC voltage. Unlike that in a two-level converter, the MI in the MMC topology plays a role in making the converter a voltage source using a capacitor. The circulating current in the MMC distorts the AC voltage reference, and the distortion affects the MI. In addition, the AC network conditions, such as AC voltage variation and reactive power, affect the MI. Therefore, the MI should be optimized with consideration of internal and external factors. This study proposes a method to optimize the MI of an MMC HVDC system.

Improved Modulation Scheme for Medium Voltage Modular Multi-level Converter Operated in Nearest Level Control (근사레벨제어로 동작하는 중전압 모듈형 멀티레벨 컨버터의 개선된 전압변조기법)

  • Kim, Do-Hyun;Kim, Jae-Hyuk;Han, Byung-Moon
    • The Transactions of the Korean Institute of Power Electronics
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    • v.22 no.4
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    • pp.285-296
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    • 2017
  • This paper proposes an improved modulation scheme for the medium voltage modular multi-level converter (MMC), which operates in the nearest level control and applies in the medium voltage direct current (MVDC) system. In the proposed modulation scheme, the offset (neutral-to-zero output) voltage is adjusted, with the phase voltage magnitude, thereby maintaining a constant value with N+1 level in the controllable modulation index (MI) range. In order to confirm the proposed scheme's validity, computer simulations for the 22.9 kV - 25 MVA MMC were performed with PSCAD/EMTDC, as well as hardware experiments for the 380 V - 10 kVA MMC. The proposed modulation scheme offers to build a constant pole voltage regardless of the MI value, and to build a phase voltage with improved total harmonic distortion (THD).

Overmodulation Operation of SVM for NPC Type 3-Level Inverter (NPC형 3레벨 인버터의 공간벡터 과변조운전)

  • Lee, Jae-Moon;Choi, Jae-Ho
    • The Transactions of the Korean Institute of Power Electronics
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    • v.13 no.1
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    • pp.22-32
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    • 2008
  • This paper proposes a linearization technique for the 3-level NPC type inverter, which increases the linear control range of Inverter up to the one-pulse inverter. The overmodulation range is divided into two modes depending on the Modulation Index, MI. In overmodulation region I, the reference angles are derived from the fourier series expansion of the reference voltage corresponding to the MI. In overmodulation region II, the holding angles are also derived in the same way. Therefore, it is possible to obtain the linear control and the maximized utilization of PWM inverter output voltage.

Reconfigurable Selective Harmonic Elimination Technique for Wide Range Operations in Asymmetric Cascaded Multilevel Inverter

  • Kavitha, R;Rani, Thottungal
    • Journal of Power Electronics
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    • v.18 no.4
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    • pp.1037-1050
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    • 2018
  • This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

SVPWM Overmodulation Scheme of Three-Level Inverters for Vector Controlled Induction Motor Drives

  • Kwon, Kyoung-Min;Lee, Jae-Moon;Lee, Jin-Mok;Choi, Jae-Ho
    • Journal of Power Electronics
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    • v.9 no.3
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    • pp.481-490
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    • 2009
  • This paper describes a SVPWM overmodulation scheme of NPC type three-level inverter for traction drives which extends the modulation index from MI=0.907 to unity. SVPWM strategy is organized by two operation modes of under-modulation and over-modulation. The switching states under the under-modulation modes are determined by dividing them with two linear regions and one hybrid region the same as the conventional three-level inverter. On the other hand, under the over-modulation mode, they are generated by doing it with two over-modulation regions the same as the conventional over-modulation strategy of a two level inverter. Following the description of over-modulation scheme of a three-level inverter, the system description of a vector controlled induction motor for traction drives has been discussed. Finally, the validity of the proposed modulation algorithm has been verified through simulation and experimental results.

A Generalized Loss Analysis Algorithm of Power Semiconductor Devices in Multilevel NPC Inverters

  • Alemi, Payam;Lee, Dong-Choon
    • Journal of Electrical Engineering and Technology
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    • v.9 no.6
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    • pp.2168-2180
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    • 2014
  • In this paper, a generalized power loss algorithm for multilevel neutral-point clamped (NPC) PWM inverters is presented, which is applicable to any level number of multilevel inverters. In the case of three-level inverters, the conduction loss depends on the MI (modulation index) and the PF (power factor), and the switching loss depends on a switching frequency, turn-on and turn-off energy. However, in the higher level of inverters than the three-level, the loss of semiconductor devices cannot be analyzed by conventional methods. The modulation depth should be considered in addition, to find the different conducting devices depending on the MI. In a case study, the power loss analysis for the three- and five-level NPC inverters has been performed with the proposed algorithm. The validity of the proposed algorithm is verified by simulation for the three-and five-level NPC inverters and experiment for three-level NPC inverter.

Performance Analysis of a Novel Reduced Switch Cascaded Multilevel Inverter

  • Nagarajan, R.;Saravanan, M.
    • Journal of Power Electronics
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    • v.14 no.1
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    • pp.48-60
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    • 2014
  • Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

Experimental and Numerical Analysis of a Simple Core Loss Calculation for AC Filter Inductor in PWM DC-AC Inverters

  • Lee, Kyoung-Jun;Cha, Honnyong;Lee, Jong-Pil;Yoo, Dong-Wook;Kim, Hee-Je
    • Journal of Power Electronics
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    • v.13 no.1
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    • pp.113-121
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    • 2013
  • This paper introduces a simple core loss calculation method for output filter inductor in pulse width modulation (PWM) DC-AC inverter. Amorphous C-core (AMCC-320) is used to analyze the core loss. In order to measure core loss of the output filter inductor and validate the proposed method, a single-phase half-bridge inverter and a calorimeter are used. By changing switching frequency and modulation index (MI) of the inverter, core loss of the AMCC-320 is measured with the lab-made calorimeter and the results are compared with calculated core loss. The proposed method can be easily extended to other core loss calculation of various converters.

Comparative Analysis of Power Losses for Three-Level T-Type and NPC PWM Inverters (3-레벨 T-형 및 NPC 인버터의 전력 손실 비교 분석)

  • Alemi, Payam;Lee, Dong-Choon
    • The Transactions of the Korean Institute of Power Electronics
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    • v.19 no.2
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    • pp.173-183
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    • 2014
  • In this paper, an analysis of power losses for the three-level T-type and neutral-point clamped (NPC) PWM inverters is presented, in which the conduction and switching losses of semiconductor devices of the inverters are taken into account. In the inverter operation, the conduction loss depends on the modulation index (MI) and power factor (PF), whereas the switching loss depends on the switching frequency. Power losses for the T-type and NPC inverters are analyzed and calculated at the different operating points of MI, PF and the switching frequency, in which the four different models of semiconductor devices are adopted. In the case of lower MI, the NPC-type is more efficient than the T-type, and vice versa. The validity of the power loss analysis has been verified by the simulation results.

Scheme for Reducing Harmonics in Output Voltage of Modular Multilevel Converters with Offset Voltage Injection

  • Anupom, Devnath;Shin, Dong-Cheol;Lee, Dong-Myung
    • Journal of Power Electronics
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    • v.19 no.6
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    • pp.1496-1504
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    • 2019
  • This paper proposes a new THD reduction algorithm for modular multilevel converters (MMCs) with offset voltage injection operated in nearest level modulation (NLM). High voltage direct current (HVDC) is actively introduced to the grid connection of offshore wind powers, and this paper deals with a voltage generation technique with an MMC for wind power generation. In the proposed method, third harmonic voltage is added for reducing the THD. The third harmonic voltage is adjusted so that each of the pole voltage magnitudes maintains a constant value with a maximum number of (N+1) levels, where N is the number of sub-modules per arm. By using the proposed method, the THD of the output voltage is mitigated without increasing the switching frequency. In addition, the proposed method has advantageous characteristics such as simple implementation. As a part of this study, this paper compares the THD results of the conventional method and the proposed method with offset voltage injection to reduce the THD. In this paper, simulations have been carried out to verify the effectiveness of the proposed scheme, and the proposed method is implemented by a HILS (Hardware in the Loop Simulation) system. The obtained results show agreement with the simulation results. It is confirmed that the new scheme achieved the maximum level output voltage and improved the THD quality.