• 제목/요약/키워드: Modular reduction

검색결과 134건 처리시간 0.033초

Design, Development and Testing of the Modular Unmanned Surface Vehicle Platform for Marine Waste Detection

  • Vasilj, Josip;Stancic, Ivo;Grujic, Tamara;Music, Josip
    • Journal of Multimedia Information System
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    • 제4권4호
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    • pp.195-204
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    • 2017
  • Mobile robots are used for years as a valuable research and educational tool in form of available open-platform designs and Do-It-Yourself kits. Rapid development and costs reduction of Unmanned Air Vehicles (UAV) and ground based mobile robots in recent years allowed researchers to utilize them as an affordable research platform. Despite of recent developments in the area of ground and airborne robotics, only few examples of Unmanned Surface Vehicle (USV) platforms targeted for research purposes can be found. Aim of this paper is to present the development of open-design USV drone with integrated multi-level control hardware architecture. Proposed catamaran - type water surface drone enables direct control over wireless radio link, separate development of algorithms for optimal propulsion control, navigation and communication with the ground-based control station. Whole design is highly modular, where each component can be replaced or modified according to desired task, payload or environmental conditions. Developed USV is planned to be utilized as a part of the system for detection and identification of marine and lake waste. Cameras mounted to the USV would record sea or lake surfaces, and recorded video sequences and images would be processed by state-of-the-art computer vision and machine learning algorithms in order to identify and classify marine and lake waste.

Effects of Peroxides on the Properties of Reclaimed Polypropylene/Waste Ground Rubber Tire Composites Prepared by a Twin Screw Extrusion

  • Kim, Seonggil;Lee, Minji;Lee, Hyeongsu;Jeong, Hobin;Park, Yuri;Jhee, Kwang-Hwan;Bang, Daesuk
    • Elastomers and Composites
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    • 제51권1호
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    • pp.17-23
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    • 2016
  • In this study, the reclaimed polypropylene (RPP) and waste ground rubber tire (WGRT) were used to simulate the thermoplastic vulcanizate (TPV) for cost reduction and resources recycling. Also, we examined the effects of dicumyl peroxide (DCP) and 2,5-dimethyl-2,5-di-(tert-butylperoxy)-hexane (DTBPH) as peroxide type cross-linking agents to enhance the properties of TPV's. The components of RPP and WGRT were fixed at 30 and 70 wt%, and DCP and DTBPH were added in the concentrations from 0.5 to 1.5 phr, respectively. RPP/WGRT composites with different contents of DCP and DTBPH were prepared by a modular intermeshing co-rotating twin screw extruder. The Young's modulus of composites were decreased with increasing peroxides contents. On the other hand, tensile strength, elongation at break, and impact strength of the composites were increased with peroxide contents. We also confirmed that interfacial adhesion between RPP and WGRT was considerably improved by adding the peroxides. Taken together, DTBPH added RPP/WGRT composites exhibited better mechanical properties rather than those of DCP added composites.

NIST P-521 타원곡선을 지원하는 고성능 ECC 프로세서 (A High-Performance ECC Processor Supporting NIST P-521 Elliptic Curve)

  • 양현준;신경욱
    • 한국정보통신학회논문지
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    • 제26권4호
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    • pp.548-555
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    • 2022
  • 본 논문은 타원곡선 디지털 서명 알고리듬 (Elliptic Curve Digital Signature Algorithm; ECDSA)의 핵심 연산으로 사용되는 타원곡선 암호 (Elliptic Curve Cryptography; ECC)의 하드웨어 구현에 대해 기술한다. 설계된 ECC 프로세서는 NIST P-521 곡선 상의 8가지 연산 모드 (점 연산 4가지, 모듈러 연산 4가지)를 지원한다. 점 스칼라 곱셈 (PSM)에 필요한 연산량을 최소화하기 위해 5가지 PSM 알고리듬과 4가지 좌표계에 따른 연산 복잡도 분석을 토대로 radix-4 Booth 인코딩과 수정된 자코비안 좌표계를 적용하여 설계하였다. 모듈러 곱셈은 수정형 3-Way Toom-Cook 정수 곱셈과 수정형 고속 축약 알고리듬을 적용하여 구현되었다. 설계된 ECC 프로세서는 xczu7ev FPGA 디바이스에 구현하여 하드웨어 동작을 검증하였다. 101,921개의 LUT와 18,357개의 플립플롭 그리고 101개의 DSP 블록이 사용되었고, 최대 동작주파수 45 MHz에서 초당 약 370번의 PSM 연산이 가능한 것으로 평가되었다.

강과 콘크리트의 합성 부재 용접시 콘크리트 강도 저감 방지 기법 연구 (A Study on Method for The Reduction of Decreasing Strength of Concrete When Welding the Connection Part of Composite Structure Consist of Steel and Concrete)

  • 원덕희;한택희;이동준;강영종
    • 한국구조물진단유지관리공학회 논문집
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    • 제13권4호통권56호
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    • pp.116-125
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    • 2009
  • 최근 건설 기술 발달에 따라 공기 단축을 위하여 세그먼트를 공장 제작하고 현장에서 용접 또는 볼팅 등의 방법으로 접합을 하는 시공이 이루어지고 있으며, 확대되고 있는 추세이다. 이때 강과 콘크리트로 구성된 합성부재의 용접시, 용접열이 약 20,000$^{\circ}C, 용접부 주변 온도가 1,300$^{\circ}C 이상이 될 정도로 높은 온도가 생성 된다. 이때 높은 온도로 인하여 용접부와 맞닿아 있는 콘크리트의 강도 감소가 발생하며, 경우에 따라서 국부적으로 강도감소가 매우 큰 곳도 존재하게 되어 구조물 거동에 영향을 미칠 수 있다. 본 연구에서는 이를 방지하기 위해 강재와 콘크리트 사이에 보강재를 삽입하여 용접열에 의한 콘크리트의 강도 감소를 방지하는 방법을 제시하였다.

GF($P^{nm}$)상의 다항식 분할에 의한 병렬 승산기 설계 (A Parallel Multiplier By Mutidigit Numbers Over GF($P^{nm}$))

  • 오진영;윤병희나기수김흥수
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 추계종합학술대회 논문집
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    • pp.771-774
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    • 1998
  • In this paper proposes a new bit-parallel structure for a multiplier over GF((Pn)m), with k-nm. Mastrovito Multiplier, Karatsuba-ofman algorithm are applied to the multiplication of polynomials over GF(2n). This operation has a complexity of order O(k log p3) under certain constrains regardig k. A complete set of primitive field polynomials for composite fields is provided which perform modulo reduction with low complexity. As a result, multiplier for fields GF(Pk) with low gate counts and low delays are constructed. The architectures are highly modular and thus well suited for VLSI implementation.

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Design of M-Channel IIR Uniform DFT Filter Banks Using Recursive Digital Filters

  • Dehghani, M.J.;Aravind, R.;Prabhu, K.M.M.
    • ETRI Journal
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    • 제25권5호
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    • pp.345-355
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    • 2003
  • In this paper, we propose a method for designing a class of M-channel, causal, stable, perfect reconstruction, infinite impulse response (IIR), and parallel uniform discrete Fourier transform (DFT) filter banks. It is based on a previously proposed structure by Martinez et al. [1] for IIR digital filter design for sampling rate reduction. The proposed filter bank has a modular structure and is therefore very well suited for VLSI implementation. Moreover, the current structure is more efficient in terms of computational complexity than the most general IIR DFT filter bank, and this results in a reduced computational complexity by more than 50% in both the critically sampled and oversampled cases. In the polyphase oversampled DFT filter bank case, we get flexible stop-band attenuation, which is also taken care of in the proposed algorithm.

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A novel design of DC-DC converter for photovoltaic PCS

  • Park, Sung-Joon
    • Journal of information and communication convergence engineering
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    • 제7권2호
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    • pp.107-112
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    • 2009
  • Renewable energy resources will be an increasingly important part of power generation in the new millennium. Besides assisting in the reduction of the emission of greenhouse gases, they add the much needed flexibility to the energy resource mix by decreasing the dependence on fossil fuels. Due to their modular characteristics, ease of installation and because they can be located closer to the user, PV system have great potential as distributed power source to the utilities. In this paper, a dc-de power converter scheme with the push-pull based technology is proposed to apply for solar power system which has many features such as high efficiency, stable output, and low acoustic noises, DC-DC converter is used in proposed topology has stable efficiency curve at all load range and very high efficiency characteristics. This paper presents the design of a single-phase photovoltaic inverter model and the simulation of its performance.

High Performance Implementation of SGCM on High-End IoT Devices

  • Seo, Hwajeong
    • Journal of information and communication convergence engineering
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    • 제15권4호
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    • pp.212-216
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    • 2017
  • In this paper, we introduce novel techniques to improve the high performance of AE functions on modern high-end IoT platforms (ARM-NEON), which support SIMD and cryptography instruction sets. For the Sophie Germain Counter Mode of operation (SGCM), counter modes of encryption and prime field multiplication are required. We chose the Montgomery multiplication for modular multiplication. We perform Montgomery multiplication in a parallel way by exploiting both the ARM and NEON instruction sets. Specifically, the NEON instruction performed 128-bit integer multiplication and the ARM instruction performed Montgomery reduction, simultaneously. This approach hides the latency for ARM in the NEON instruction set. For a high-speed counter mode of encryptions for both AE functions, we introduced two-level computations. When the tasks were large volume, we switched to the NEON instruction to execute the encryption operations. Otherwise, we performed the encryptions on the ARM module.

외란 관측기를 이용한 견실한 차량 안정성 제어 (Robust Vehicle Stability Control Using Disturbance Observer)

  • 한진오;이경수;강수준;이교일
    • 대한기계학회논문집A
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    • 제26권12호
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    • pp.2519-2526
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    • 2002
  • A disturbance observer-based vehicle stability controller is proposed in this paper. The lumped disturbance to the vehicle yaw rate dynamics caused by the uncertain factors such as uncertain tire forces and parameters is estimated by the disturbance observer, which is utilized by the robust controller to stabilize the lateral dynamics of the vehicle. The dynamics of the hydraulic actuator is incorporated in the vehicle stability controller design using the model reduction technique. Modular control design methodology is adopted to effectively deal with the mismatched uncertainty. Simulation results indicate that the proposed disturbance observer-based vehicle stability controller can achieve the desired reference tracking performance as well as sufficient level of robustness.

GF($q^n$)상의 병렬 승산기 설계를 위한 기약다항식에 관한 연구 (A Study on Irreducible Polynomial for Construction of Parallel Multiplier Over GF(q$^{n}$ ))

  • 오진영;김상완;황종학;박승용;김홍수
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 하계종합학술대회 논문집
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    • pp.741-744
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    • 1999
  • In this paper, We represent a low complexity of parallel canonical basis multiplier for GF( q$^{n}$ ), ( q> 2). The Mastrovito multiplier is investigated and applied to multiplication in GF(q$^{n}$ ), GF(q$^{n}$ ) is different with GF(2$^{n}$ ), when MVL is applied to finite field. If q is larger than 2, inverse should be considered. Optimized irreducible polynomial can reduce number of operation. In this paper we describe a method for choosing optimized irreducible polynomial and modularizing recursive polynomial operation. A optimized irreducible polynomial is provided which perform modulo reduction with low complexity. As a result, multiplier for fields GF(q$^{n}$ ) with low gate counts. and low delays are constructed. The architectures are highly modular and thus well suited for VLSI implementation.

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