• The Transactions of the Korean Institute of Power Electronics
• /
• v.22 no.6
• /
• pp.476-483
• /
• 2017

In this paper, a voltage-based model predictive control (MPC) scheme for a modular multilevel converter is used to reduce switching loss. The proposed method calculates an offset voltage that clamps the switching operation of submodules in which the current greatly flows at every sampling period by using the reference phase voltage and the reference phase current. To use the offset voltage, the proposed method converts the current-based MPC to the voltage-based MPC. The proposed voltage-based MPC then generates a new reference pole voltage that clamps the switching of submodules by applying the calculated offset voltage to the phase voltage. Therefore, the proposed method can reduce the switching loss by stopping the switching operation of submodules in which the current greatly flows. The switching loss reduction effect of the proposed method is verified by comparing its loss data with those of the conventional MPC method.

• Journal of Power Electronics
• /
• v.19 no.6
• /
• pp.1496-1504
• /
• 2019

This paper proposes a new THD reduction algorithm for modular multilevel converters (MMCs) with offset voltage injection operated in nearest level modulation (NLM). High voltage direct current (HVDC) is actively introduced to the grid connection of offshore wind powers, and this paper deals with a voltage generation technique with an MMC for wind power generation. In the proposed method, third harmonic voltage is added for reducing the THD. The third harmonic voltage is adjusted so that each of the pole voltage magnitudes maintains a constant value with a maximum number of (N+1) levels, where N is the number of sub-modules per arm. By using the proposed method, the THD of the output voltage is mitigated without increasing the switching frequency. In addition, the proposed method has advantageous characteristics such as simple implementation. As a part of this study, this paper compares the THD results of the conventional method and the proposed method with offset voltage injection to reduce the THD. In this paper, simulations have been carried out to verify the effectiveness of the proposed scheme, and the proposed method is implemented by a HILS (Hardware in the Loop Simulation) system. The obtained results show agreement with the simulation results. It is confirmed that the new scheme achieved the maximum level output voltage and improved the THD quality.

• Nuclear Engineering and Technology
• /
• v.53 no.11
• /
• pp.3580-3596
• /
• 2021

An integral test facility, PILLAR, was commissioned, aiming to provide valuable experimental results which can be referenced by system and component designers and used for the performance demonstration of liquid-metal-cooled, passive small modular reactors (SMRs) toward their licensing. The setup was conceptualized by a scaling analysis which allows the vertical arrangements to be conserved from its prototypic reactor, scaled uniformly in the radial direction achieving a flow area reduction of 1/200. Its final design includes several heater rods which simulate the reactor core, and a single heat exchanger representing the steam generators in the prototype. The system behaviors were characterized by its data acquisition system implementing various instruments. In this paper, we present not only a detailed description of the facility components, but also selected experimental results of both steady-state and transient cases. The obtained steady-state test results were utilized for the benchmark of a system code, achieving a capability of accurate simulations with ±3% of maximum deviations. It was followed by qualitative comparisons on the transient test results which indicate that the integral system behaviors in passive LBE-cooled systems are able to be predicted by the code.

• The KIPS Transactions:PartC
• /
• v.17C no.2
• /
• pp.145-152
• /
• 2010

In this paper, we first propose a fast division algorithm in GF($2^{163}$) using standard basis representation, and then it is mapped into divider for GF($2^{163}$) with iterative hardware structure. The proposed algorithm is based on the binary ExtendedGCD algorithm, and the arithmetic operations for modular reduction are performed within only one "while-statement" unlike conventional approach which uses two "while-statement". In this paper, we use reduction polynomial $f(x)=x^{163}+x^7+x^6+x^3+1$ that is recommended in SEC2(Standards for Efficient Cryptography) using standard basis representation, where degree m = 163. We also have implemented the proposed iterative architecture in FPGA using Verilog HDL, and it operates at a clock frequency of 85 MHz on Xilinx-VirtexII XC2V8000 FPGA device. From implementation results, we will show that computation speed of the proposed scheme is significantly improved than the existing two approaches.

• Korean Journal of Construction Engineering and Management
• /
• v.16 no.6
• /
• pp.3-11
• /
• 2015

The current real estate market is in a state that is considerably shrink due to the recession and long-term reduction of trading. In response, the government recently announced an innovative way for the middle-class residential housing and it is taking the lead to activate the real estate market. Meanwhile, the domestic housing market is entering a transition period, including structural changes of household structure, changes from joeonse to rent increasingly. Also single-member households will rise steeply, so that makes the high demand of small houses. In addition, the domestic construction industry is interested in new technology called Modular building. The Modular construction is an off-site construction system that shorten construction period, eco-friendly building technology and mobility etc, which can be used in various field. Overall, there are two major issues of the current market, one is the change of the real estate market, and the other is the modular construction. This study will propose modular business model in the rental market through the analysis the profitability of the modular business scenarios and IRR analysis.

• Journal of the Korean Society of Systems Engineering
• /
• v.17 no.2
• /
• pp.69-81
• /
• 2021

The human performance issues and increased automation issues in advanced Small Modular Reactors (SMRs) are critical to numerous stakeholders in the nuclear industry, due to the undesirable implications targeting the Man Machine Interface Systems (MMIS) complexity of (Generation IV) SMRs. It is imperative that the design of future SMRs must address these problems. Nowadays, Multi Agent Systems (MAS) are used in the industrial sector to solve multiple complex problems; therefore incorporating this technology in the proposed innovative SMR (I-SMR) design will contribute greatly in the decision making process during plant operations, also reduce the number MCR operating crew and human errors. However, it is speculated that an increased level of complexity will be introduced. Prior to achieving the objectives of this research, the tools used to analyze the system for complexity reduction, are the McCabe's Cyclomatic complexity metric and the Henry-Kafura Information Flow metric. In this research, the systems engineering approach is used to guide the engineering process of complexity reduction concept of the system in its entirety.

• Proceedings of the KIPE Conference
• /
• 2011.11a
• /
• pp.185-186
• /
• 2011

본 논문에서는 최근 직류송전용 컨버터로 많은 관심이 집중되고 있는 모듈형 멀티레벨 컨버터(Modular Multi-level Converter)에서 출력파형의 고조파를 저감하는 모듈레이션 방법과 각 모듈의 직류전압 불평형을 해소하는 알고리즘에 대해 기술하고 있다. 먼저 본 논문에서 임의의 개수로 반브리지 모듈이 주어졌을 때 고조파 레벨이 최소화되도록 다펄스 형태로 출력파형을 형성하는 방식을 제안하고 그 타당성을 PSCAD 소프트웨어를 이용한 시뮬레이션으로 검증하였다. 이 방식은 다펄스 출력파형의 각 계단을 형성하는 모듈의 턴온과 턴오프 시점을 보편화된 수식으로 정하는 방식으로 알고리즘 구현이 매우 용이하다. 또한 각 모듈의 직류전압 불평형을 바로잡는 알고리즘을 제안하고 그 타당성도 시뮬레이션으로 검증하였는데, 이 방식은 각 모듈이 교류 매 반주기마다 생성하는 펄스의 크기를 순차적으로 형성하는 것으로 알고리즘의 구현이 용이하다. 본 논문에서 제안하는 알고리즘은 향후 국내에서 모듈형 멀티레벨 컨버터를 개발할 때 유용하게 활용될 것으로 보인다.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.16 no.2
• /
• pp.1-9
• /
• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• Proceedings of the KIPE Conference
• /
• 2014.11a
• /
• pp.11-12
• /
• 2014

This paper introduces a scaled hardware model for the 10kVA, 1kV, 11-level MMC (Modular Multilevel Converter), which was manufactured in the lab based on computer simulations with PSCAD/EMTDC. Various experiments were conducted to verify the major operation algorithms of MMC. The hardware scaled-model developed in the lab can be utilized for analyzing the operation analysis and performance evaluation of MMC according to the modulation pattern and redundancy operation scheme.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.18 no.1
• /
• pp.1-9
• /
• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.