• Proceedings of the KSR Conference
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• 2000.05a
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• pp.360-367
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• 2000

This paper is intended to provide a method to design control software for the TCMS, train control and monitoring system. The TCMS with this control software will be applied KOREA Standard EMU. The control software is designed by SCADE Case tool to concern safety and reliability. The function for the EMU is implemented in software easily programmed, using a functional block, graphic programming language. The control software has modular design and each module is tested with SCADE simulator. This time we focus a Driving control module, including brake control module, and present a design method and a simulation method for that module.

• Proceedings of the KSR Conference
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• 1999.11a
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• pp.302-309
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• 1999

This paper is intended to provide a method to design control software fur the TCMS, train control and monitoring system. The TCMS with this control software will be applied KOREA Standard EMU. The control software is designed by SCADE Case tool to concern safety and reliability. The function for the EMU is implemented in software easily programmed, using a functional block, graphic programming language. the control software has modular design and each module is tested with SCADE simulator. This time we focus a HVAC(heater, ventilation and air conditioner controller) control module, present a design method and a simulation method for that module.

• Progress in Superconductivity and Cryogenics
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• v.8 no.2
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• pp.17-19
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• 2006

A novel clock distribution technique for pipelined-RSFQ logics using variable Bias Currents of JTLs as delay-medium is newly proposed. RSFQ logics consist of several logic gates or blocks connected in a pipeline structure. And each block has variable delay difference. In the structure, this clock distribution method generates a set of clock signals for each logic blocks with suitable corresponding delays. These delays, in the order of few to tens of pS, can be adjusted through controlling bias current of JTL of delay medium. While delays with resistor value and JJ size are fixed at fabrication stage, delay through bias current can be controlled externally, and thus, is heavily investigated for its range as well as correct operation within current margin. Possible ways of a standard delay library with modular structure are sought for further modularizing Pipelined-RSFQ applications. Simulations and verifications are done through WRSpice with Hypres 3-um process parameters.

• Journal of IKEEE
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• v.23 no.4
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• pp.1321-1327
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• 2019

This paper describes an efficient hardware implementation of modular square root (MSQR) computation over GF(p), which is the operation needed to map plaintext messages to points on elliptic curves for elliptic curve (EC)-ElGamal public-key encryption. Our method supports five sizes of elliptic curves over GF(p) defined by the National Institute of Standards and Technology (NIST) standard. For the Koblitz curves and the pseudorandom curves with 192-bit, 256-bit, 384-bit and 521-bit, the Euler's Criterion based on the characteristic of the modulo values was applied. For the elliptic curves with 224-bit, the Tonelli-Shanks algorithm was simplified and applied to compute MSQR. The proposed method was implemented using the finite field arithmetic circuit with 32-bit datapath and memory block of elliptic curve cryptography (ECC) processor, and its hardware operation was verified by implementing it on the Virtex-5 field programmable gate array (FPGA) device. When the implemented circuit operates with a 50 MHz clock, the computation of MSQR takes about 18 ms for 224-bit pseudorandom curves and about 4 ms for 256-bit Koblitz curves.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.15-25
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• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.33 no.5
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• pp.311-318
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• 2020

This study introduces a technique for improving the elastomeric-isolator performance using modular devices. The modular devices are shear resistance block, polymer spring, displacement acceptance guide, and anti-falling block. They are installed on the elastomeric isolator as a supplementary device. Each modularized device improves the isolator performance by performing step-by-step actions according to the seismic intensity and displacement. The PRB isolation device works in four stages, depending on the seismic magnitude, to satisfy the target performance. It is designed to accommodate design displacement in the first stage and large magnitude of earthquakes in the second and third stages. This design prevents superstructures from falling in the fourth stage due to large-magnitude earthquakes by increasing the capacity limit of the elastomeric isolator. In this study, the PRB isolation device is analyzed using finite element analysis to verify that the PRB isolation device works as intended and it can withstand loads corresponding to large-magnitude earthquakes. The performance of the PRB isolation device is validated by the analysis, which is further corroborated by actual experiments.

• Elastomers and Composites
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• v.39 no.2
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• pp.131-141
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• 2004

The recycling of waste XLPE(crosslinked polyethylene), which is a major source of scraps from high voltage power transmission cables, has been discussed. The waste XLPE scraps were ground into fine powder with various sizes from less than $100{\mu}m$ up to about $1000{\mu}m$ using two types of tailor-made pulverizers. The compounds were prepared in a modular intermeshing co-rotating twin screw extruder at various conditions such as different compositions, types and powder sizes of waste XLPE, screw configurations and various polymer matrices (LDPE, HDPE, PP, PS). The mechanical and rheological properties and the fracture surface or the compounds were investigated. It was found that an improved impact strength was obtained from the compound with white XLPE powder pulverized from the scraps without outer/inner semi-conductive layers. Generally, the impact strength increases with the content of XLPE but decreases with the size of XLPE. Especially for LDPE, the extrusion was possible up to 80 wt% loading of XLPE. Also, the impact strength increases with the number of kneading disc blocks in the given screw configurations. The melt viscosity of the compounds increases with increasing XLPE loading. However, the higher shear thinning behavior of the compounds at common shear rates implies proper processibility of the compounds. In addition, the impact strength for other polymer matrices used increases with XLPE and it is noticeable that the impact strength of PS/XLPE (80/20 wt%) compound was improved twice that of pure PS.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.8
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• pp.796-804
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• 1992

This paper presents a design of a backbone network which uses a rigister-Insertion ring structure, The introduction of a high speed register in sertton backbone ring enables high performance inter-network 4ommunicatlons In a simple and modular structure at low cost and Its concurrent communications.. Two or more bridge nodes can be used to construct a register Insertion backbone ring network. The high bandwidth of the backbone ring sup ports heavy traffic for Inter-segment Eornrnunicatlons. The bridge node does both local address filtering to block data entering the ring and remote address filtering to block data entering the local LAN segment . Title local address greatly reduces the rate on the backbone ring and the remote address filterlng greatly reduces the traffic rate on each LAN segment. An feature makes the network the network reconflguratlon simpler and transparent to users. A throughput analysis Is used to deterrune the bandwidth of the backbone rlr)g transmission medium.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1470-1476
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• 2020

This paper describes a design of a lightweight security system-on-chip (SoC) suitable for the implementation of security protocols for IoT and mobile devices. The security SoC using Cortex-M0 as a CPU integrates hardware crypto engines including an elliptic curve cryptography (ECC) core, a SHA3 hash core, an ARIA-AES block cipher core and a true random number generator (TRNG) core. The ECC core was designed to support twenty elliptic curves over both prime field and binary field defined in the SEC2, and was based on a word-based Montgomery multiplier in which the partial product generations/additions and modular reductions are processed in a sub-pipelining manner. The H/W-S/W co-operation for elliptic curve digital signature algorithm (EC-DSA) protocol was demonstrated by implementing the security SoC on a Cyclone-5 FPGA device. The security SoC, synthesized with a 65-nm CMOS cell library, occupies 193,312 gate equivalents (GEs) and 84 kbytes of RAM.

• Structural Engineering and Mechanics
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• v.17 no.3_4
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• pp.393-408
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• 2004

There exists a clear need to monitor the performance of civil structures over their operational lives. Current commercial monitoring systems suffer from various technological and economic limitations that prevent their widespread adoption. The wires used to route measurements from system sensors to the centralized data server represent one of the greatest limitations since they are physically vulnerable and expensive from an installation and maintenance standpoint. In lieu of cables, the introduction of low-cost wireless communications is proposed. The result is the design of a prototype wireless sensing unit that can serve as the fundamental building block of wireless modular monitoring systems (WiMMS). An additional feature of the wireless sensing unit is the incorporation of computational power in the form of state-of-art microcontrollers. The prototype unit is validated with a series of laboratory and field tests. The Alamosa Canyon Bridge is employed to serve as a full-scale benchmark structure to validate the performance of the wireless sensing unit in the field. A traditional cable-based monitoring system is installed in parallel with the wireless sensing units for performance comparison.