• Journal of the Korean Geotechnical Society
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• v.23 no.6
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• pp.5-21
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• 2007

Despite a number of advantages of reinforced earth walls over conventional concrete retaining walls, there exit concerns over long-term residual deformation when they are subjected to repeated and/or cyclic loads, especially when used as part of permanent structures. In view of these concerns, in this paper time-dependant deformation characteristics of geosynthetic reinforced modular block walls under sustained anuor repeated loads were investigated using reduced-scale model tests. The results indicated that a sustained or repeated load can yield appreciable magnitude of residual deformation, and that the residual deformations are influenced not only by the loading characteristics but by the mechanical properties of geogrid. It is also found that the preloading technique can be effectively used in controlling residual deformations of reinforced soils subjected to sustained and/or repeated loads.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.793-794
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• 2011

This paper presents a method of the circuit design of the multiple-valued digital logic switching functions based on the modular techniques. Fisr of all, we introduce the necessity, background and concepts of the modular design techniques for the digital logic systems. Next, we discuss the definitions that are used in this paper. For the purpose of the circuit design for the multiple-valued digital logic switching functions, we discuss the extraction of the partition functions. Also we describe the construction method of the building block, that is called the modules, based on each partition functions. And we apply the proposed method to the example, we compare the results with the results of the earlier methods. In result, we decrease the control functions, it means that we obtain the effective cost in the digital logic design for any other earlier methods. In the future research, we require the universal module that traet more partition functions and more compact module.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.11
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• pp.1663-1668
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• 2017

A BLDC motor with higher number of phases has several advantages, compared to the conventional three-phase BLDC motors. It can reduce the commutation torque ripple and the iron loss without increasing the voltage per phase and increase the reliability and power density. Higher number of phases increase the torque-per-ampere ratio for the same machine volume and output power by widening the electrical conduction period. In this paper, the proposed seven-phase BLDC motor drive system is made into several functional modular blocks, so that it can be easily extended to other ac motor applications: back-EMF block, hysteresis current control block, pwm inverter block, phase current block, and speed/torque control block. Also in a system of BLDC motor drive, the PI controller has been widely used in the speed controller because of the simple implementation. To obtain a good speed response in a general drive system using the PI controller, the high bandwidth of a controller is established. therefore, in this paper, a Fuzzy controller is applied to the 7-phase BLDC motor drive system in order to improve the speed control performance. The Fuzzy controller is compared with a conventional PI controller through the experiment with respect to speed dynamic responses. These experimental results show that the Fuzzy controller of the 7-phase BLDC motor drive system is superior over the conventional PI controller. The algorithm using the Fuzzy controller can improve a comfortable ride in the field of high performance 7-phase BLDC motor drive applications.

• Journal of the Korean Society of Environmental Restoration Technology
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• v.11 no.6
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• pp.26-37
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• 2008

The purpose of the study was to evaluate the effect of pervious pavements on reducing the surface runoff caused by rainfall. The surface runoff from twelve steel experimental beds with different pavement had been recorded every minute from May to September 2008, by the measuring system of tipping buckets(0.1mm/count) and data aquisition systems(National Instrument's Labview and DAQ boards & Autonics PR12-4). The dimension of the experimental bed was $1.5m(W){\times}2.0m(L){\times}0.6m(D)$ and eleven different kinds of vegetational(grass, grass+cubic stone, grass+hole brick), modular(brick, cubic stone, small cubic stone, wood block, interlocking block, clay brick, granular clay brick) and granular(naked soil, gravel) paving materials and concrete were applied for the comparison. Six rain events with depth over 30mm were selected and compared. The maximum depth of the rainfall selected was 137.5mm for 28 hours, and the minimum 30mm for 5 hours. The maximum rainfall per hour was 23mm/hr and the minimum 11.4mm/hr. The major findings were as follows; 1. All pervious pavement applied reduced over 75% of the surface runoff compared with concrete pavement. The grassy and porous pavements were relatively efficient in reducing surface runoff. 2. The grass was the more efficient as intercepting average 69.5mm of initial surface runoff, and maximum 77.8mm at the condition of 13.5mm/hr rainfall. The next was gravel intercepting maximum 65.5mm at the condition of 13.5mm/hr and the 40.9mm at 19.1mm/hr, average 55.7mm. 3. The modular pavements common in urban area were not good in intercepting the runoff except the 'clay granular brick' compared with others. The 'clay granular brick' showed relatively efficient intercepting average 14.1mm, which was the bigger amount than the 'grass+hole brick'. 4. The 'naked soil' were more effective than the 'concrete', 'brick', and 'interlocking block' in reducing the surface runoff, but less efficient than other materials. The capacity of the 'naked soil' to intercept the initial rainfall was similar to the 'brick'. As summary, the more grassy and porous pavement shows more effective in reducing surface runoffs.

• ETRI Journal
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• v.33 no.2
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• pp.267-274
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• 2011

This paper proposes an efficient masking method for the block cipher SEED that is standardized in Korea. The nonlinear parts of SEED consist of two S-boxes and modular additions. However, the masked version of these nonlinear parts requires excessive RAM usage and a large number of operations. Protecting SEED by the general masking method requires 512 bytes of RAM corresponding to masked S-boxes and a large number of operations corresponding to the masked addition. This paper proposes a new-style masked S-box which can reduce the amount of operations of the masking addition process as well as the RAM usage. The proposed masked SEED, equipped with the new-style masked S-box, reduces the RAM requirements to 288 bytes, and it also reduces the processing time by 38% compared with the masked SEED using the general masked S-box. The proposed method also applies to other block ciphers with the same nonlinear operations.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.626-628
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• 2004

This paper describes an 8-bit CMOS folding A/D converter for set-top box. Modular low-power, high-speed CMOS A/D converter for embedded systems aims at design techniques for low-power, high-speed A/D converter processed by the standard CMOS technology. The time-interleaved A/D converter or flash A/D converter are not suitable for the low-power applications. The two-step or multi-step flash A/D converters need a high-speed SHA, which represents a tough task in high-speed analog circuit design. On the other hand, the folding A/D converter is suitable for the low-power, high-speed applications(Embedded system). The simulation results illustrate a conversion rate of 40MSamples/s and a Power dissipation of 80mW(only analog block) at 2.5V supply voltage.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.11a
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• pp.112-115
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• 2003

모듈러 멱승은 주어진 값 X, E, N에 대하여 X$^{E}$ mod N으로 정의된다. 모듈러 멱승은 대부분의 공개키 암호시스템과 전자서명에 사용되므로, 이 연산을 빠르게 수행하는 문제는 암호학 분야에서 중요하게 연구 되고 있다. 모듈러 멱승을 계산하기 위해 가장 많이 사용되는 효율적인 알고리즘은 VLNW방법이다. 그러나 이 방법은d, q 인자를 고정시키기 때문에 제한적인 결과를 제공한다. 일반화된 그래프 모델은 VLNW방법의 f 인자를 제거하여 그 성능을 향상시켰다. 그러나 고 인자는 여전히 VLNW방법과 동일하게 고정되어 있다. d 인자는 초기 블록 테이블을 결정하는 인자로써, 이것을 확장할 경우 천 처리 시간이 기하급수적으로 증가하게 된다. 그러나, 본 논문은 전 처리 시간의 기하급수적인 증가를 저지하면서도 고 인자를 확장하기 위해서 초기 블록 테이블을 만드는 몇 가지 효율적인 방법을 제시한다. 이 방법은 VLNW 방법과 일반화된 그래프 모델보다도 효율적이며, 그 성능은 실험을 통하여 검증하였다.

• Proceedings of the KSR Conference
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• 1999.05a
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• pp.259-266
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• 1999

This paper is intended to provide a method to design control software for the TCMS, train control and monitoring system. The TCMS with this control software will be applied KOREA Standard EMU. The control software is designed by SCADE Case tool to concern safety and reliability. The function for the EMU is implemented in software easily programmed, using a functional block, graphic programming language. The control software has modular design and each module is tested with SCADE simulator. This time we focus a door control module, present a design method and a simulation method for that module.

• Review of KIISC
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• v.5 no.2
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• pp.97-101
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• 1995

지난 세번에 걸쳐 소개하던 실체인증기법을 중단하고 이번호 부터는 해쉬함수 국제표준을 소개한다. 국내에서도 표준화 노력이 진행되고 있는 해쉬함수는 임의의 길이의 비트스트링을 정해진 길이의 출력인 해쉬코드로 변환시키는 함수로서 디지탈서명, 인증. 키 분배등의 많은 적용사례를 갖고 있다. 해쉬함수의 표준화 과제는 1984년 디지탈서명 국제표준화 과제중 한 part로 시작했다가 1989년 독립된 과제가 되었다 그 당시에는 2개의 part(Part 1 : General. Part 2 : Hash-functions using an n-bit block cipher algorithm)로 시작되었다가 나중에 2개의 part (Part 3 : Dedicated hash-functions, Part 4 : Hash-functions using modular arithmetic)가 추가되었다. 이 과제는 1991년 CD(Committee Draft), 1992년 DIS(Draft for International Standard)가 되었고. 1993년에 IS(International Standard)가 되었고 1998년 1차 검토가 있을 예정이다.