• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2013년도 춘계학술대회 논문집
• /
• pp.965-966
• /
• 2013

• 한국멀티미디어학회논문지
• /
• 제3권1호
• /
• pp.77-90
• /
• 2000

실시간 검증은 명세와 요구사항과의 논리적 정확성 뿐만 아니라 시간적 정확성을 확인하는 일련의 과정이다. 하지만 시간의 무한성에 의해 시스템 상태가 무한히 증가할 수 있는 상태 폭발 문제가 검증과정에서 중요한 문제점이 되고 있다. 본 논문에서는 형식 검증에 기반을 두며, 시스템의 행위 측면을 시간 오토마타로 기술한 시스템 모델이 Timed mu-calculus로 표현된 시스템의 특성에 만족하는지의 여부를 통해 명세의 완전성을 확인하는 실시간 검증 비법을 기술한다. 이를 위해 초기상태의 논리값에 초점을 두어 검증과정에서 필요로 하는 노드로만 Product Graph를 구성하여 노드 값을 결정해나가는 지역모형검사 기법에 대해 제안한다. 이 방법은 모델의 모든 상태를 조사하지 않으므로 상태 폭발 문제를 최소화 시킬 수 있어 실시간 시스템 검증에 효과적으로 적용이 가능하다.

• Nuclear Engineering and Technology
• /
• 제46권3호
• /
• pp.381-386
• /
• 2014

A highly reliable safety class controller for NPPs (Nuclear Power Plants) is mandatory as even a minor malfunction can lead to disastrous consequences for people, the environment or the facility. In order to enhance the reliability of a safety class digital controller for NPPs, we employed a diversity approach, in which a PLC-type controller and a PLD-type controller are to be operated in parallel. We built and used structured testbenches based on the classes supported by UVM for functional verification of the PLD-type controller designed for NPPs. We incorporated a UVM register model into the testbenches in order to increase the controllability and the observability of the DUT(Device Under Test). With the increased testability, we could easily verify the datapaths between I/O ports and the register sets of the DUT, otherwise we had to perform black box tests for the datapaths, which is very cumbersome and time consuming. We were also able to perform constrained random verification very easily and systematically. From the study, we confirmed the various advantages of using the UVM register model in verification such as scalability, reusability and interoperability, and set some design guidelines for verification of the NPP controllers.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1998년도 추계종합학술대회 논문집
• /
• pp.755-758
• /
• 1998

As the performance of microprocessor improves, the design complexity grows exponentially. Therefor, it is very important to make the bug-free model as early as possible in a design life-cycle. This paper describes the simulation-based functional verification methodology for the RTL level description model. It is performed by multi-stage verification methods using extensive hand-generated self-checking tests supplemented with random tests. This approach is opplied to the functional verification of the GPU processor of Raptor and various bugs are detected.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
• /
• pp.939-942
• /
• 2003

Design verification problem is emerging as an important issue to detect any design errors at the early stage of the design. Conventionally, design verifications have been done using a simulation technique. However, this technique has been proved not to cover all potential design errors. Therefore, formal technique is often used to verify digital circuits as an alternative. In this paper we adopted formal verification technique and verified some important properties derived from our pipelined digital systems, using SMV (Symbolic Model Verifier). Our example shows that model checking method (one of formal verification techniques) can be effectively performed in verifying the large digital systems.

• 한국수산과학회지
• /
• 제30권6호
• /
• pp.964-973
• /
• 1997

A tidal prism eutrophication model, an one-dimensional intertidal model, is developed to study water quality conditions at small coastal basins and tidal creeks. The model simulates the physical transport processes using the concept of tidal flushing. The concept is simple and straightforward, and thus is ideal for small coastal basins with complex geometry. The model, having twenty-four state variables in the water column, simulates salinity, temperature, dissolved oxygen, three algal groups, and the cycles of carbon, nitrogen, phosphorus and silica. The model is applied to the Lynnhaven Bay, a small coastal basin of Chesapeake Bay in U.S.A. The model is calibrated using the field data collected in 1994, and then is verified using the independently collected data in 1980. The model overall gives a good reproduction of the field data, partly owing to the data collected from the field surveys specifically designed for the model application. This paper presents the procedure, and the results of the model calibration and verification.

• 음성과학
• /
• 제14권2호
• /
• pp.127-135
• /
• 2007

Feature vectors of speech are generally extracted from whole frequency domain. The inherent character of a speaker is located in the low band or high band frequency. However, if the speech is corrupted by narrowband noise with concentrated energy, speaker verification performance is reduced as the individual characteristic is removed. In this paper, we propose a PCA Covariance Model based on the multiband to extract the robust feature vectors against the narrowband noise. First, we divide the overall frequency band into several subbands. Second, the correlation of feature vectors extracted independently from each subband is removed by PCA. The distance obtained from each subband has different distribution. To normalize against the different distribution, we moved the value into the normalized distribution through the mapping function. Finally, the represented value applying the weighting function is used for speaker verification. In the experiments, the proposed method shows better performance of the speaker verification and reduces the computation.

• 한국IT서비스학회지
• /
• 제10권3호
• /
• pp.189-201
• /
• 2011

Feature models are widely used to model commonalities and variabilities among products during software product line development. Feature configurations are generated by selecting the features to be included in individual products. Automated tools to identify errors or inconsistencies in the feature models and configurations are essential to successful software product line engineering. This paper proposes a verification technique and tool based on semantic web technologies such as OWL, SWRL and Protege API. This approach checks the feature model and configuration based on predefined rules and provides information on existence of errors as well as the kinds of those errors. This approach is extensible due to ease of rule modification and may be easily applied to other environments because semantic web technologies can be easily integrated with other programming environments. This paper demonstrates how various semantic web-related technologies can support automatic verification of one kind of software development artifact, the feature model.

• Journal of Biosystems Engineering
• /
• 제23권6호
• /
• pp.549-560
• /
• 1998

The dynamic model of a tractor-trailer system developed in the first part of this paper was verified in this article by comparing the simulated acceleration responses of the system with actually measured ones. A commercially available tractor and a trailer were used for the verification test. Values of the model parameters were measured or theoretically derived if the measurement was practically impossible. The tractor-trailer system was operated with different forward speeds over three equally spaced half-sine bumps on the flat concrete surface. Results of the verification tests showed that autospectra of the measured and simulated accelerations of the tractor-trailer system agreed well up to the frequencies slightly feater than the fundamental frequencies of the ground excitations and at the frequencies of engine excitations. The mean of normalized errors of the simulated responses to the measured ones was estimated to be less than 10% for all the test runs. The peak responses in the autospectra also coincided well both in the frequency and magnitude.

• 한국시뮬레이션학회:학술대회논문집
• /
• 한국시뮬레이션학회 2005년도 춘계학술대회 논문집
• /
• pp.100-105
• /
• 2005

Development of complex discrete event simulators requires cooperation between domain experts and modeling experts who involve the development. With the cooperation the domain experts derive user requirement and modeling experts transform the requirement to a simulation model. This paper proposes a method for consistency verification of simulation model in DEVS formalism against the user requirement in UML diagrams. It also presents an automated tool, called VeriDEVS, which implements the proposed method. Inputs of VeriDEVS are three UML diagrams, namely use case, class and sequence diagrams, and DEVS Graph, all in Visio; outputs of a verification result is represented in PowerPoint files.