• Journal of KIISE:Software and Applications
• /
• v.34 no.8
• /
• pp.743-751
• /
• 2007

Model checking has been successfully applied to hardware verification. Software is more subtle than hardware with respect to formal verification due to its infinite state space. Although there are many research activities in this area, bounded model checking is regarded as a promising technique. Bounded model checking uses an upper bound to unroll its model, which is the main advantage of bounded model checking compared to other model checking techniques. In this paper, we applied bounded model checking to verify BIR which is the input model for the model checking tool BOGOR. Some BIR examples are verified with our technique. Experimental results show that bounded model checking is better than explicit model checking provided by BOGOR. This paper presents the formalization of BIR and the encoding algorithm of BIR into CNF.

• Journal of Computing Science and Engineering
• /
• v.3 no.4
• /
• pp.260-277
• /
• 2009

In this paper we propose a model for checking integrity constraints of mobile databases called Three-Level (3-L) model, wherein the process of constraint checking to maintain the consistent state of mobile databases is realized at three different levels. Sufficient and complete tests proposed in the previous works together with the idea of caching relevant data items for checking the integrity constraints are adopted. This has improved the checking mechanism by preventing delays during the process of checking constraints and performing the update. Also, the 3-L model reduces the amount of data accessed given that much of the tasks are performed at the mobile host, and hence speeds up the checking process.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.10
• /
• pp.2310-2316
• /
• 2010

This paper presents an application of retiming to model checking, a branch of formal verification. Retiming can change the transition relation of a circuit without changing its input-output behaviour by relocating its registers. With the retiming, a given circuit can have a different structure more adequate for model checking. This paper proposes a cost function to reflect the number of registers and the characteristic of its transition relation and develops a heuristic annealing algorithm to search efficiently the circuit structures obtained by retiming. Experimental results show that the proposed method can improve the model checking performance.

• International Journal of Advanced Culture Technology
• /
• v.9 no.3
• /
• pp.352-359
• /
• 2021

The purpose of this study is to design and build fake news discrimination systems and methods using fact-checking guidelines. In other words, the main content of this study is the system for identifying fake news using Artificial Intelligence -based Fact-checking guidelines. Specifically planned guidelines are needed to determine fake news that is prevalent these days, and the purpose of these guidelines is fact-checking. Identifying fake news immediately after seeing a huge amount of news is inefficient in handling and ineffective in handling. For this reason, we would like to design a fake news identification system using the fact-checking guidelines to create guidelines based on pattern analysis against fake news and real news data. The model will monitor the fact-checking guideline model modeled to determine the Fact-checking target within the news article and news articles shared on social networking service sites. Through this, the model is reflected in the fact-checking guideline model by analyzing news monitoring devices that select suspicious news articles based on their user responses. The core of this research model is a fake news identification device that determines the authenticity of this suspected news article. So, we propose news article identification methods with fact-checking guideline on Artificial Intelligence & Bigdata. This study will help news subscribers determine news that is unclear in its authenticity.

• Journal of KIISE:Software and Applications
• /
• v.30 no.7_8
• /
• pp.642-648
• /
• 2003

In this paper, we are interested in checking equivalence of FSMs(finite state machines). Two FSMs are equivalent if and only if their responses are always equal with each other with respect to the same external stimuli. Equivalence checking FSMs makes complicated FSM be substituted for simpler one, if they are equivalent. We can also determine the system satisfies the requirements, if they are all written in FSMs. In this paper, we regard equivalence checking problem as model checking one. For doing so, we construct the product model $M ={M_A} {\beta}{M_B} from two FSMs ${M_A} and {M_B}$. And we also get the temporal logic formula ${\Phi}$ from the equivalence checking definition. Then, we can check with model checker whether if satisfies ${\Phi}$, written $M= {.\Phi}$. Two FSMs are equivalent, if $M= {.\Phi}$ Otherwise, it is not equivalent. In that case, model checker generates counterexamples which explain why FSMs are not equivalent. In summary, we solve the equivalence checking problem with model checking techniques. As a result of applying to several examples, we have many satisfiable results.

• Journal of KIISE:Software and Applications
• /
• v.31 no.11
• /
• pp.1560-1567
• /
• 2004

In temporal logic model checking, the number of states is exponentially increased by the size of a model. This is called the state explosion problem. Abstraction, partial order, symmetric, etc. are widely used to avoid the problem. They reduce a number of states by exploiting structural information in a model. Instead, this paper proposes the relay model checking that decomposes a temporal formula to be verified into several sub-formulas and then model checking them one by one. As a result, we solve complex games that can't handle with previous techniques.

• Journal of KIISE
• /
• v.44 no.10
• /
• pp.1034-1044
• /
• 2017

Although traversal strategies are important for the performance of model checking, many studies have ignored the impact of traversal strategies in model checking with a block-encoded abstract reachability graph. Studies have considered traversal strategies only for an abstract reachability graph without block-encoding. Block encoding plays a crucial role in the model checking performance. This paper therefore describes Dual-traversal strategy, a simple and novel technique to control traversal strategies in a block-encoded abstract reachability graph. This method uses two traversal strategies for a model checking, one for effective block-encoding, and the other for traversal in an encoded abstract reachability graph. Dual-traversal strategy is very simple and can be implemented without overhead compared to the existing single-traversal strategy. We implemented the Dual-traversal strategy in an open source model checking tool and compare the performances of different traversal strategies. The results show that the model checking performance varies from the traversal strategies for the encoded abstract reachability graph.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
• /
• v.25 no.11
• /
• pp.631-639
• /
• 2013

This study derives quality checking items in Building Mechanical Systems Design Criteria, and suggests quality criteria to review BIM models in the duct system of an air conditioning system for rule-based automatic checking. First, components for the duct system of an air conditioning system were reviewed, and the quality checking items were drawn from Building Mechanical Systems Design Criteria, through assessment according to object, attribute and relationship composing the BIM model. Second, quality checking types were derived, by analyzing the quality checking items and Rule set of the Solibri Model Checker. Finally, methods of algorithm functioning for checking the BIM models for mechanical systems in computers were drawn, and Elements to comprise the quality checking criteria (rule) were suggested. This study means that that checking items are derived from domestic criteria, and a way for the development process of determining quality checking criteria (rules) is suggested.

• The KIPS Transactions:PartD
• /
• v.12D no.1 s.97
• /
• pp.81-90
• /
• 2005

Given a model and a property, model checking determines whether the model satisfies the property. In case the model does not satisfy the property model checking gives a counterexample which explains where the violation occurs. Since counterexamples are useful for model debugging as well as model understanding, counterexample generation is one of the indispensable components in the model checking tool. This paper presents efficient counterexample generation techniques when a safety property is falsified. These techniques are used to solve Push Push games which consist of 50 games. As a result, all the games are solved with the proposed techniques. However, with the original NuSMV, 42 games are solved but 8 failed. In addition, we obtain $86{\%}$ time improvement and $62{\%}$ space improvement compared to the original NuSMV in solving the game.

• Journal of the Korea Society of Computer and Information
• /
• v.18 no.1
• /
• pp.123-136
• /
• 2013

The Feature model can not be guaranteed the syntactic accuracy of its model and be difficult the validation using automatic tool for its syntax, because this model is expressed by a graphical and informal structure in itself. Therefore, there is a need to formalize and check for the feature model, to precisely define syntax for construct of the model. This paper presents a Z formal specification and a model checking mechanism of the feature model to guarantee the correctness of the model. It first defines the translation rules between feature model and Z, and then converts the syntax of the feature model into the Z schema specification by applying these rules. Finally, the Z schema specification is checked syntax, type, and domain errors using the Z/Eves validation tool to assure the correctness of its specification, With the use of the proposed method, we may express more precisely the construct of the feature model. Moreover the domain analyst are able to usefully verify the errors of the generated feature model.