Equivalence Checking of Finite State Machines with SMV

SMV를 이용한 유한 상태 기계의 동치 검사

  • 권기현 (경기대학교 정보과학부) ;
  • 엄태호 (경기대학교 전자계산학과)
  • Published : 2003.08.01

Abstract

In this paper, we are interested in checking equivalence of FSMs(finite state machines). Two FSMs are equivalent if and only if their responses are always equal with each other with respect to the same external stimuli. Equivalence checking FSMs makes complicated FSM be substituted for simpler one, if they are equivalent. We can also determine the system satisfies the requirements, if they are all written in FSMs. In this paper, we regard equivalence checking problem as model checking one. For doing so, we construct the product model $M ={M_A} {\beta}{M_B} from two FSMs ${M_A} and {M_B}$. And we also get the temporal logic formula ${\Phi}$ from the equivalence checking definition. Then, we can check with model checker whether if satisfies ${\Phi}$, written $M= {.\Phi}$. Two FSMs are equivalent, if $M= {.\Phi}$ Otherwise, it is not equivalent. In that case, model checker generates counterexamples which explain why FSMs are not equivalent. In summary, we solve the equivalence checking problem with model checking techniques. As a result of applying to several examples, we have many satisfiable results.

본 연구에서는 유한 상태 기계들 간의 동치 여부를 검증하고자 한다. 즉 모든 입력에 대하여 유한 상태 기계의 반응이 항상 동일한지를 판정하고자 한다. 만약 두 개의 유한 상태 기계가 동치라고 판정된다면, 복잡한 유한 상태 기계는 단순한 기계로 대치될 수 있다. 또한 명세와 구현이 모두 유한 상태 기계로 표현된 경우, 동치 검사를 이용해서 구현이 명세를 만족하는지 결정할 수 있다. 본 논문에서는 이와 같은 유한 상태 기계의 동치 검사를 모델 검사 기법으로 다음과 같이 해결한다. 주어진 유한 상태 기계${M_A}와 {M_R}$를 조합하여 모델 $M = {M_A} {\times} {M_\beta}$을 구축하고, 검사할 동치 조건을 시제 논리식 ${\Phi}$로 기술한다. 만일 모델이 시제 논리식을 만족한다면$(M={\Phi})$ 두 기계는 동치이다. 그렇지 않다면 두 기계는 비동치이며 그 이유를 설명하는 반례를 제공한다. 전 과정이 자동화되었으며, 여러 개의 사례 연구에 적용한 결과 만족할 만한 결과를 얻었다.

Keywords

References

  1. R. Skvarcius and W.B. Robinson, Discrete Mathematics with Computer Science Applications, The Benjamin/Cummings Publishing Company, 1986
  2. D. Harel and A. Naamad, 'The STATEMATE Semantics of Statecharts,' ACM Transactions on Software Engineering and Methodology, Vol.5, No.4, pp.293-333, 1996 https://doi.org/10.1145/235321.235322
  3. David Y.W. Park, et.al., 'Static Analysis to Identify Invariants in RSML Specifications,' In Proceedings of Formal Techniques in Real-Time and Fault-Tolerant'98, LNCS 1486, 1998 https://doi.org/10.1007/BFb0055343
  4. C. Heitmeyer, et.al., 'Using Abstraction and Model Checking to Detect Safety Violations in Requirements Specifications,' IEEE Transactions on Software Engineering, Vol.24, No.11, 1998 https://doi.org/10.1109/32.730543
  5. S.Y. Huang, K.T. Cheng, K.C. Chen, C.Y. Huang, and F. Brewer, 'AQUILA: An Equivalence Checking System for Large Sequential Designs,' IEEE Transactions on Computer, Vol.49, No.5, pp.443-464, 2000 https://doi.org/10.1109/12.859539
  6. Robert Meolic, Tatjana Kapus, Zmago Brezocnik, 'Computing Testing Equivalence with Binary Decision Diagrams,' In Proceedings of the Seventh Electrotechnical and Computer Science Conference ERK'98, pp.51-54, 1998
  7. E.M. Clarke, O. Grumberg, and D. Peled, Model Checking, MIT Press, 1999
  8. M. Huth and M. Ryan, Logic in Computer Science: Modelling and Reasoning about Systems, Cambridge University Press, 2000
  9. E.M. Clarke, E.A. Emerson, and A.P. Sistla, 'Automatic Verification of Finite-State Concurrent Systems using Temporal Logic Specifications,' ACM Transactions on Programming Languages and Systems, Vol.8, No.2, pp.244-263, 1986 https://doi.org/10.1145/5397.5399
  10. K.L. McMillan, 'Symbolic Model Checking: An approach to the state explosion problem,' PhD thesis, Carnegie Mellon University, 1992
  11. C.A.J. van Eijk and J.A.G. Jess, 'Detection of Equivalent State Variables in Finite State Machine Verification,' In Proceedings of the 1995 ACM/IEEE International Workshop on Logic Synthesis, pp. 3.35-3.44, 1995
  12. C.A.J. van Eijk and J.A.G. Jess, 'Exploiting Functional Dependencies in Finite State Machine Verification,' In Proceedings of the European Design and Test Conference ED&TC, pp.9-14, 1996 https://doi.org/10.1109/EDTC.1996.494119
  13. A. Biere, A. Cimatti, E.M. Clarke, and Y. Zhu, 'Symbolic Model Checking without BDDs,' in Proceedings of Tools and Algorithms for the Analysis and Construction of Systems (TACAS'99), LNCS 1579 , 1999