• Journal of Mechanical Science and Technology
• /
• v.20 no.1
• /
• pp.1-12
• /
• 2006

This work reviews the effects of catalyst formulation and exhaust gas composition on soot oxidation in CDPF (Catalytic Diesel Particulate Filter). DOC's (Diesel Oxidation Catalysts) have been loaded with Pt catalyst (Pt/$Al_{2}O_3$) for reduction of HC and CO. Recent CDPF's are coated with the Pt catalyst as well as additives like Mo, V, Ce, Co, Fe, La, Au, or Zr for the promotion of soot oxidation. Alkali (K, Na, Cs, Li) doping of metal catalyst tends to increase the activity of the catalysts in soot combustion. Effects of coexistence components are very important in the catalytic reaction of the soot. The soot oxidation rate of a few catalysts are improved by water vapor and NOx in the ambient. There are only a few reports available on the mechanism of the PM (particulate matter) oxidation on the catalysts. The mechanism of PM oxidation in the catalytic systems that meet new emission regulations of diesel engines has yet to be investigated. Future research will focus on catalysts that can not only oxidize PM at low temperature, but also reduce NOx, continuously self-cleaning diesel particulate filters, and selective catalysts for NOx reduction.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.205-207
• /
• 2008

The new process for hybrid silicon thin film transistor (TFT) using DPSS laser has been developed for realizing both low-temperature poly-Si (LTPS) TFT and a-Si:H TFT on the same substrate as a backplane of active matrix liquid crystal display. LTPS TFTs are integrated on the peripheral area of the panel for gate driver integrated circuit and a-Si:H TFTs are used as a switching device for pixel in the active area. The technology has been developed based on the current a-Si:H TFT fabrication process without introducing ion-doping and activation process and the field effect mobility of $4{\sim}5\;cm^2/V{\cdot}s$ and $0.5\;cm^2/V{\cdot}s$ for each TFT was obtained. The low power consumption, high reliability, and low photosensitivity are realized compared with amorphous silicon gate driver circuit and are demonstrated on the 14.1 inch WXGA+ ($1440{\times}900$) LCD Panel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.82-82
• /
• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.26 no.11
• /
• pp.785-789
• /
• 2013

Silicon Carbide (SiC) is the material with the wide band-gap (3.26 eV), high critical electric field (~2.3 MV/cm), and high bulk electron mobility (~900 $cm^2/Vs$). These electronic properties allow attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. In general, device design has a significant effect on the switching and electrical characteristics. It is known that in this paper, we demonstrated that the switching performance and breakdown voltage of IGBT is dependent with doping concentration of p-base region and drift layer by using 2-D simulations. As a result, electrical characteristics of SiC-IGBT deivce is higher breakdown voltage ($V_B$= 1,600 V), lower on-resistance ($R_{on}$= 0.43 $m{\Omega}{\cdot}cm^2$) than Si-IGBT. Also, we determined that processing time and cost is reduced by the depth of n-drift region of IGBT was reduced.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.20 no.12
• /
• pp.1022-1026
• /
• 2007

We have demonstrated new functionalities of Ag doped chalcogenide glasses based on their capabilities as solid electrolytes. Formation of such amorphous systems by the introduction of silver via photo-induced diffusion in thin chalcogenide films is considered. The influence of silver on the properties of the newly formed materials is regarded in terms of diffusion kinetics and Ag saturation is related to the composition of the hosting material. Silver saturated chalcogenide glasses have been used in the formation of solid electrolyte which is the active medium in programmable metallization cell (PMC) devices. In this paper, we investigated electrical and optical properties of Ag-doped chalcogenide thin film on changed thickness of Ag and chalcogenide thin films, which is concerned at Ag-doping effect of PMC cell. As a result, when thickness of Ag and chalcogenide thin film was 30 nm and 50 nm respectively, device have excellent characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.133-133
• /
• 2008

Recently, as the down-scailing of field-effect transistor devices continues, Schottky-barrier field-effect transistors (SB-FETs) have attracted much attention as an alternative to conventional MOSFETs. SB-FETs have advantages over conventional devices, such as low parasitic source/drain resistance due to their metallic characteristics, low temperature processing for source/drain formation and physical scalability to the sub-10nm regime. The good scalability of SB-FETs is due to their metallic characteristics of source/drain, which leads to the low resistance and the atomically abrupt junctions at metal (silicide)-silicon interface. Nevertheless, some reports show that SB-FETs suffer from short channel effect (SCE) that would cause severe problems in the sub 20nm regime.[Ouyang et al. IEEE Trans. Electron Devices 53, 8, 1732 (2007)] Because source/drain barriers induce a depletion region, it is possible that the barriers are overlapped in short channel SB-FETs. In order to analyze the SCE of SB-FETs, we carried out systematic studies on the Schottky barrier overlapping in short channel SB-FETs using a SILVACO ATLAS numerical simulator. We have investigated the variation of surface channel band profiles depending on the doping, barrier height and the effective channel length using 2D simulation. Because the source/drain depletion regions start to be overlapped each other in the condition of the $L_{ch}$~80nm with $N_D{\sim}1\times10^{18}cm^{-3}$ and $\phi_{Bn}$ $\approx$ 0.6eV, the band profile varies as the decrease of effective channel length $L_{ch}$. With the $L_{ch}$~80nm as a starting point, the built-in potential of source/drain schottky contacts gradually decreases as the decrease of $L_{ch}$, then the conduction and valence band edges are consequently flattened at $L_{ch}$~5nm. These results may allow us to understand the performance related interdependent parameters in nanoscale SB-FETs such as channel length, the barrier height and channel doping.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.18 no.6
• /
• pp.253-257
• /
• 2008

To enhance the luminescence properties, the red phosphor composed of $(Y,\;Zn)_2O_3$:$Eu^{3+}$ as doping concentration of Zn ion is synthesized at $1200^{\circ}C$ for 6 hrs in air atmosphere by conventional solid reaction method. As a result of the red phosphor $(Y,\;Zn)_2O_3$:$Eu^{3+}$ is measured X-ray diffraction (XRD), The main peak is nearly corresponded to the same as JCPDS card (No. 41-1105). When the doping concentration of Zn ion is more than 5 mol%, However, the ZnO peak is showed by XRD analysis. Therefore, when the doping concentration of Zn ion is less than 5 mol%, the Zn ion is well mixed in $Y_2O_3$ structure without the impurity phases. The photoluminescence (PL) properties is shown as this phosphor is excited in 254 nm region and the highest emission spectra of $(Y,\;Zn)_2O_3$:$Eu^{3+}$ has shown in 612 nm region because of a typical energy transition ($^5D_0{\rightarrow}^7F_2$) of $Eu^{3+}$ ion. As the doping concentration of Zn ion is more than 10 mol%, the emission peak is suddenly decreased. when the highest emission peak as doping concentration of Zn ion is shown, the composition of this phosphor is $(Y_{0.95},\;Zn_{0.05})_2O_3$:$Eu^{3+}_{0.075}$ and the particle size analyzed by FE-SEM is confirmed from 0.4 to $3{\mu}m$.

• Journal of Information Display
• /
• v.10 no.1
• /
• pp.33-36
• /
• 2009

A new hybrid silicon thin-film transistor (TFT) fabrication process using the DPSS laser crystallization technique was developed in this study to realize low-temperature poly-Si (LTPS) and a-Si:H TFTs on the same substrate as a backplane of the active-matrix liquid crystal flat-panel display (AMLCD). LTPS TFTs were integrated into the peripheral area of the activematrix LCD panel for the gate driver circuit, and a-Si:H TFTs were used as a switching device of the pixel electrode in the active area. The technology was developed based on the current a-Si:H TFT fabrication process in the bottom-gate, back-channel etch-type configuration. The ion-doping and activation processes, which are required in the conventional LTPS technology, were thus not introduced, and the field effect mobility values of $4\sim5cm^2/V{\cdot}s$ and $0.5cm^2/V{\cdot}s$ for the LTPS and a-Si:H TFTs, respectively, were obtained. The application of this technology was demonstrated on the 14.1" WXGA+(1440$\times$900) AMLCD panel, and a smaller area, lower power consumption, higher reliability, and lower photosensitivity were realized in the gate driver circuit that was fabricated in this process compared with the a-Si:H TFT gate driver integration circuit

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.131-131
• /
• 2008

Silicon carbide (SiC) has attracted significant attention for high frequency, high temperature and high power devices due to its superior properties such as the large band gap, high breakdown electric field, high saturation velocity and high thermal conductivity. We performed Al ion implantation processes on n-type 4H-SiC substrate using a SILVACO ATHENA numerical simulator. The ion implantation model used a Monte-Carlo method. We studied the effect of channeling by Al implantation simulation in both 0 off-axis and 8 off-axis n-type 4H-SiC substrate. We have investigated the Al distribution in 4H-SiC through the variation of the implantation energies and the corresponding ratio of the doses. The implantation energies controlled 40, 60, 80, 100 and 120 keV and the implantation doses varied from $2\times10^{14}$ to $1\times10^{15}cm^{-2}$. In the simulation results, the Al ion distribution was deeper as increasing implantation energy and the doping level increased as increasing implantation doses. After the post-implantation annealing, the electrical properties of Al-implanted p-n junction diode were investigated by SILV ACO ATLAS numerical simulator.