• Proceedings of the KIEE Conference
• /
• 1994.07b
• /
• pp.1451-1453
• /
• 1994

A monolithic current limiting power MOSFET, which may be easily fabricated by the conventional DMOS process, is proposed. The proposed current limiting MOSFET consists of main power cells, sensing cells, and NPN lateral bipolar transistor so that users can adjust the current limiting levels with only one external resistor. The behaviors of the proposed device are numerically simulated and analyzed by 2-D device simulator MEDICI and mixed-mode simulator CA-AAM(Circuit Analysis Advanced Application Module).

• The Journal of Society for e-Business Studies
• /
• v.23 no.3
• /
• pp.1-12
• /
• 2018

Mixed-criticality systems consist of components with different criticality. Recently, components are categorized depending on criticality by ISO 26262 standard and DO-178B standard in automotive and avionic domain. Existing mixed-criticality system research achieved efficient and safe scheduling through system-level criticality mode. The drawback of these approaches is performance degradation of low-criticality tasks on high-criticality mode. Task-level criticality mode is one method to address the problem and improve the performance of low-critical tasks. In this paper, we propose probabilistic performance metric for the approach. In simulation results with probabilistic performance metric, we showed that our approach has better performance than the existing approaches.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.131-131
• /
• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.24 no.2 s.173
• /
• pp.370-377
• /
• 2000

This paper presents a mixed-mode type ER(electro-rheological) engine mount, and its vibration control performance for a passenger vehicle is presented. The field-dependent yield stress of a transfo rmer oil-based ER fluid is empirically distilled in both shear and flow modes. This is then incorporated with the governing equation of motion of the proposed mixed-mode(shear mode plus flow mode) type engine mount. The damping force is analyzed with respect to the intensity of the electric field and design parameters such as electrode gap. Subsequently, the ER engine mount which is equivalent to the conventional hydraulic engine mount in terms of the damping level is designed and manufactured. Both computer simulation and experimental test are undertaken in order to evaluate vibration isolation performance. In addition, this performance is compared with that of the conventional hydraulic engine mount.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.82-82
• /
• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

• Structural Engineering and Mechanics
• /
• v.35 no.3
• /
• pp.283-299
• /
• 2010

This paper addresses the numerical simulation of fatigue crack growth in arbitrary 2D geometries under constant amplitude loading by the using a new finite element software. The purpose of this software is on the determination of 2D crack paths and surfaces as well as on the evaluation of components Lifetimes as a part of the damage tolerant assessment. Throughout the simulation of fatigue crack propagation an automatic adaptive mesh is carried out in the vicinity of the crack front nodes and in the elements which represent the higher stresses distribution. The fatigue crack direction and the corresponding stress-intensity factors are estimated at each small crack increment by employing the displacement extrapolation technique under facilitation of singular crack tip elements. The propagation is modeled by successive linear extensions, which are determined by the stress intensity factors under linear elastic fracture mechanics (LEFM) assumption. The stress intensity factors range history must be recorded along the small crack increments. Upon completion of the stress intensity factors range history recording, fatigue crack propagation life of the examined specimen is predicted. A consistent transfer algorithm and a crack relaxation method are proposed and implemented for this purpose. Verification of the predicted fatigue life is validated with relevant experimental data and numerical results obtained by other researchers. The comparisons show that the program is capable of demonstrating the fatigue life prediction results as well as the fatigue crack path satisfactorily.

• Electrical & Electronic Materials
• /
• v.8 no.5
• /
• pp.572-579
• /
• 1995

Most of conventional ultrasonic transducers are constructed to generate either longitudinal or shear waves, but not both of them. We investigate the mechanism of dual mode transducers that generate both of the longitudinal and shear waves simultaneously with single PZT element. The study is aimed to find the optimally desired cut by examining the anisotropic piezoelectric properties. Theory predicts that a mixed P/S mode transducer can be constructed using a rotated Z-cut of PZT piezoelectric ceramics. We study the performance of a PZT element as a function of its rotation angle so that its efficiency is optimized to excite the two waves as much as equally strong. The results are verified by the waveform in pulse-echo computer simulation and experiments. When the transducer is subjected to impedance analysis, it shows two thickness mode resonances, each of which being a mixed P/S thickness mode. By examining wave speeds on E transmitter delay line receiver setup, it is confirmed that the transducer can transmit and detect both longitudinal and shear wave simultaneously.

• 전자공학회논문지 IE
• /
• v.46 no.4
• /
• pp.8-15
• /
• 2009

In this paper, we are indicated CMOS Image sensor circuit SPICE analysis for the Photo Diode and pixel Modeling. We get a characteristic of the photoelectric current using a device simulator Medici and develop the Photodiode model for applying a SPICE simulation. For verifying the result, We compared the result of SPICE simulation with the result of mixed mode simulation about the testing circuit structure consisted photodiode and NMOS.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.04b
• /
• pp.37-38
• /
• 2009

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. It is known that in SiC power MOSFET, the JFET region width is one of the most important parameters. In this paper, we demonstrated that the switching performance of DMOSFET is dependent on the with width of the JFET region by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the n JFET region, CSL, and n-drift layer. It has been found that the JFET region reduces specific on-resistance and therefore the switching characteristics depend on the JFET region.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.22 no.9
• /
• pp.737-740
• /
• 2009

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics, In this paper, we demonstrated that the switching performance of DMOSFETs are dependent on the with Channel length ($L_{channel}$) and Current Spreading Layer thickness ($T_{CSL}$) by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the JFET region, CSL, and epilayer. It is found that improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance. Therefore, accurate modeling of the operating conditions are essential for the optimizatin of superior switching performance.