• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.7
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• pp.4087-4092
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• 2014

The gangway connection of the articulated high speed railway vehicles (HSRV) is a double wrinkled rubber component to seal the air of the corridor under a range of angular deviations between the carriage end parts. From the results of non-linear structural analysis, one of the severe loading conditions for the connection is mixed mode (rolling+yawing) angular displacements while passing through the small-radius curved siding track of the HSRV depot. In this study, to ensure the safety enhancement of the component, the optimal design for the cross section of that was performed using the Solid Isotropic Material with Penalization (SIMP) method. Nonlinear finite element analysis confirmed that the decreases in the maximum principal strain of the optimized design under rolling and mixed modes are 68% and 39%, respectively, compared to the initial design.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.32 no.11
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• pp.970-977
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• 2008

This paper deals with the dynamic characteristics of the shaft with impeller model which is the most important part in developing the resin mixing machine. Through reverse engineering, it is possible to make the shaft with impeller geometry model which is necessary vibration characteristic analysis by commercial impeller. The natural frequency analysis and structural analysis using finite element analysis software are performed on the imported commercial shaft with impeller model. The most important fundamental natural frequency of the shaft with impeller model is around 14.5 Hz, which well agrees with modal testing. The most effective design variables were extracted by ANOM(analysis of means) and pareto chart. This paper presents approximation 2nd order polynomial as design variables using RSM(response surface methodology). Generally, RSM take 2 or 3 design variables, but this method uses 5 design variables with table of mixed orthogonal array. Further more, the analyzed result of the commercial shaft with impeller is to be utilized for the structural design of resin chock mixing machine.

• Computational Structural Engineering
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• v.2 no.2
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• pp.62-72
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• 1989

This study presents rational methods for probability-based estimates of basic design wind speeds in Korea and proposes a risk-based nation-wide map of design wind speeds. The paper examines the fittings of the extreme Type I mode to largest yearly non-typhoon wind data from long-term records, and to largest monthly non-typhoon wind data from short-term records. For the estimation of the extreme typhoon wins speed distribution, an indirect analytical method based on a Monte-Carlo simulation is applied to typhoon-prone regions. The basic desig wind speeds for typhoon and non-typhoon winds at the sites of concern are made to be obtained from the mixed model given as a product of the two distributions. The results of this study show that the proposed models and methods provide a practicable tool for the development of the risk-based basic design wind speed and the design wind map from short-term station records currently available in Korea.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.55-55
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.9 s.100
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• pp.957-963
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• 2005

This paper presents technique of wideband TIA for optical communication systems using TSMC 0.25 ${\mu}m$ CMOS RF-Mixed mode. In order to improve bandwidth characteristics of an TIA, we use active inductor shunt peaking to cascode and common-source configuration. The result shows the 37 mW and 45 mW power dissipation with 2.5 V bias and 61 dB$\Omega$ and 61.4 dB$\Omega$ transimpedance gain. And the -3 dB bandwidth of the TIA is enhanced from 0.8 GHz to 1.45 GHz in cascode and 0.61 GHz to 0.9 GHz in common-source. And the input noise current density is $5 pA/\sqrt{Hz}$ and $4.5 pA/\sqrt{Hz}$, and -10 dB out put return loss is obtained in 1.45 GHz. The total size of the chip is $1150{\times}940{\mu}m^2$.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.247-252
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• 2009

This paper presents an Integer-N phase-locked loop (PLL) frequency synthesizer using a novel prescaler based on a charge pump and clock triggering circuit. A quadrature VCO has been designed for the 900MHz UHF RFID application. In this circuit, a voltage-controlled oscillator(VCO), a novel Prescaler, phase frequency detector(PFD), charge pump(CP), and analog lock detector(ALD) have been integrated with 0.35-${\mu}m$CMOS process. The integer divider has been developed with a verilog-HDL module, and the PLL mixed mode simulation has been performed with Spectre-Verilog co-simulator. The sweep range of VCO is designed from 828 to 960 MHz and the VCO generates four phase quadrature signals. The simulation results show that the phase noise of VCO is -102dBc/Hz at 100 KHz offset frequency, and the maximum lock-in time is about 4us with 32MHz step change (from 896 to 928 MHz).

• The Journal of the Acoustical Society of Korea
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• v.18 no.5
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• pp.52-57
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• 1999

It is very important to design of QAM modulator of high spectral efficiency for high speed data transmission. In this paper, typical 16-QAM modulator is designed by modification design of DDFS(direct digital frequency synthesizer). DDFS generates sinusoidal waveform digitally to the frequency setting word. Phase modulation is accuratly made by control of a generated phase increment value and amplitude modulation is accomplished in the D/A converter output by control of amplitude level. For the suppression of harmonics and glitch, dual-structured DDFS is studied to improve the spurious characteristics. P-Spice is used for design and simulation in mixed mode. Also we can get the satisfactory results of designed 16-QAM modulator from the constellation output.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.503-504
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• 2006

This paper presents the design and fabrication of a LC voltage-controlled oscillator (VCO) using 1-poly 6-metal mixed signal CMOS process. To obtain the high-quality factor inductor in LC resonator, patterned-ground shields (PGS) is placed under the symmetric inductor to reduce the effect from image current of resistive Si substrate. Moreover, due to the incapability of using thick top metal layer of which the thickness is over $2{\mu}m$, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via materials along the metal traces is adopted. The circuit operated from 2.63 GHz to 3.09 GHz tuned by accumulation-mode MOS varactor. The corresponding tuning range was 460 MHz. The measured phase noise was -115 dBc/Hz @ 1MHz offset at 2.63 GHz carrier frequency and the current consumption and the corresponding power consumption were about 2.6 mA and 4.68 mW respectively.

• Wind and Structures
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• v.37 no.6
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• pp.445-460
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• 2023

Accurate estimation of modal parameters (i.e., natural frequency, damping ratio) of tall buildings is of great importance to their structural design, structural health monitoring, vibration control, and state assessment. Based on the combination of variational mode decomposition, smoothed discrete energy separation algorithm-1, and Half-cycle energy operator (VMD-SH), this paper presents a method for structural modal parameter estimation. The variational mode decomposition is proved to be effective and reliable for decomposing the mixed-signal with low frequencies and damping ratios, and the validity of both smoothed discrete energy separation algorithm-1 and Half-cycle energy operator in the modal identification of a single modal system is verified. By incorporating these techniques, the VMD-SH method is able to accurately identify and extract the various modes present in a signal, providing improved insights into its underlying structure and behavior. Subsequently, a numerical study of a four-story frame structure is conducted using the Newmark-β method, and it is found that the relative errors of natural frequency and damping ratio estimated by the presented method are much smaller than those by traditional methods, validating the effectiveness and accuracy of the combined method for the modal identification of the multi-modal system. Furthermore, the presented method is employed to estimate modal parameters of a full-scale tall building utilizing acceleration responses. The identified results verify the applicability and accuracy of the presented VMD-SH method in field measurements. The study demonstrates the effectiveness and robustness of the proposed VMD-SH method in accurately estimating modal parameters of tall buildings from acceleration response data.

• The Journal of the Acoustical Society of Korea
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• v.16 no.3
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• pp.106-113
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• 1997

A 3V CMOS continuous-time fully-balanced integrator for low-voltage analog-digital mixed-mode signal processing is designed in this paper. The basic architecture of the designed fully-balanced integrator is complementary circuit which is composed of NMOS and PMOS transistor. And this complementary circuit can extend transconductance of an integrator. So. the unity gain frequency, pole and zero of integrator are increased by the extended transconductance. The SPICE simulation and small signal analysis results show that the UGF, pole and zero of the integrator is increased larger than those of the compared integrtors. The three-pole active low-pass filter is designed as a application circuit of the fully-balanced integrator, using 0.83V CMOS processing parameter.