• Title/Summary/Keyword: Mixed Mode S-Parameter

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Mixed-mode S-parameter Measurement System of Twisted Pairs (연선의 혼합 모드 산란 계수 측정 시스템)

  • Ahn, Jungsik
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.22 no.6
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    • pp.888-894
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    • 2018
  • In this paper, we proposed a mixed-mode s-parameter measurement system for measuring the performance of twisted pairs. A twisted pair is a balanced type component, its characteristics can not be directly measured using network analyzer, which is generally implemented as a unbalanced type. It is possible to convert between balanced signal and unbalanced signal by using a balun but it restricts the frequency range of the measurement system. The proposed system measures the performance of twisted pairs by measuring mixed-mode s-parameters using a 4-port vector network analyzer and a designed fixture, without using a balun. We measured the performance of a commercial Ethernet cable and compared with the results which measured by using baluns. The results showed that the proposed system is capable of measuring the performance of twisted pairs.

Evaluation of Y-Cap Capacitance in EMI Filter Design Using Measured S-Parameter (측정된 S-파라메터를 이용한 EMI 필터의 Y-캡 용량 산정에 대한 연구)

  • Kim, Jonghyeon;Jeon, Jiwoon;Kim, Taeho;Kim, Sungjun;Nah, Wansoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.25 no.3
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    • pp.319-332
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    • 2014
  • Insertion loss is used as the character to express the efficiency of EMI filter. In this paper, we studied the better method that can measure the insertion loss of EMI filter exactly than the original method. For the achievement of this, the method measuring both common mode(CM) and differential mode(DM) insertion loss with arbitrary input/output impedance is accomplished using a 4-ports S-parameters system for consideration of unbalanced factor. Using this method, when input/output used in specific system is known, CM/DM insertion loss of EMI filter inserted in the system can be calculated. Finally, we applied 4-ports modeling method to 'X/Y capacitor part' and suggested the algorithm for selecting suitable the value of Y-capacitor using mixed mode S-parameters and mixed mode chain S-parameters.

Averaged strain energy density to assess mixed mode I/III fracture of U-notched GPPS samples

  • Saboori, Behnam;Torabi, A.R.;Berto, F.;Razavi, S.M.J.
    • Structural Engineering and Mechanics
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    • v.65 no.6
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    • pp.699-706
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    • 2018
  • In the present contribution, fracture resistance of U-notched GPPS members under mixed mode I/III loading conditions is assessed by using the Averaged Strain Energy Density (ASED) criterion. This criterion has been founded based on the ASED parameter averaged over a well-defined control volume embracing the notch edge. The validation of the theoretical criterion predictions is evaluated through comparing with the results of a series of mixed mode I/III fracture tests conducted on rectangular-shaped GPPS specimens weakened by a single edge U-notch. A recently developed apparatus for mixed mode I/III fracture experiments is employed for measuring the fracture loads of the specimens. The test samples are fabricated with different notch tip radii with the aim of evaluating the influence of this major feature of the U-notched components on the mixed mode I/III fracture behavior. It is shown that the onset of brittle fracture in U-notched GPPS specimens under various combinations of tension and out-of-plane shear can well be predicted by means of the ASED criterion.

A New Architecture of CMOS Current-Mode Analog-to-Digital Converter Using a 1.5-Bit Bit Cell (1.5-비트 비트 셀을 이용한 새로운 구조의 CMOS 전류모드 아날로그-디지털 변환기)

  • 최경진;이해길;나유찬;신홍규
    • The Journal of the Acoustical Society of Korea
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    • v.18 no.2
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    • pp.53-60
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    • 1999
  • In this paper, it is proposed to a new architecture of CMOS IADC(Current-Mode Analog-to-Digital Converter) using 1.5-bit bit cell of which consists a CSH(Current-Mode Sample-and-Hold) and CCMP(Current-Mode Comparator). In order to guarantee the entire linearity of IADC, the CSH is designed to cancel CFT(Clock Feedthrough) whose resolution is to meet at the least 9-bit which is placed in the front-end of each bit cell. In the proposed IADC, digital correction logic is simplified and power consumption is reduced because bit cell of each stage needs two latch CCMP. Also, it is available for a mixed-mode integrated circuit because all of block is designed with only MOS transistor. With the HYUNDAI 0.8㎛ CMOS parameter, the HSPICE simulation results show that the proposed IADC can be operated at 20Ms/s with SNR of 43 dB with which is satisfied 7-bit resolution for input signal at 100 ㎑, and its power consumption is 27㎽.

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Design of A 3V CMOS Fully-Balanced Complementary Current-Mode Integrator (3V CMOS Fully-Balanced 상보형 전류모드 적분기 설계)

  • Lee, Geun-Ho;Bang, Jun-Ho;Cho, Seong-Ik;Kim, Dong-Yong
    • The Journal of the Acoustical Society of Korea
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    • v.16 no.3
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    • pp.106-113
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    • 1997
  • A 3V CMOS continuous-time fully-balanced integrator for low-voltage analog-digital mixed-mode signal processing is designed in this paper. The basic architecture of the designed fully-balanced integrator is complementary circuit which is composed of NMOS and PMOS transistor. And this complementary circuit can extend transconductance of an integrator. So. the unity gain frequency, pole and zero of integrator are increased by the extended transconductance. The SPICE simulation and small signal analysis results show that the UGF, pole and zero of the integrator is increased larger than those of the compared integrtors. The three-pole active low-pass filter is designed as a application circuit of the fully-balanced integrator, using 0.83V CMOS processing parameter.

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Nonlinear vibration analysis of carbon nanotube reinforced composite plane structures

  • Rezaiee-Pajand, Mohammad;Masoodi, Amir R.;Rajabzadeh-Safaei, Niloofar
    • Steel and Composite Structures
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    • v.30 no.6
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    • pp.493-516
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    • 2019
  • This paper is dedicated to nonlinear static and free vibration analysis of Uniform Distributed Carbon Nanotube Reinforced Composite (UD-CNTRC) structures under in-plane loading. The authors have suggested an efficient six-node triangular element. Mixed Interpolation of Tensorial Components (MITC) approach is employed to alleviate the membrane locking phenomena. Moreover, the behavior of the well-known LST element is considerably improved by applying an additional linear interpolation on the strain fields. Based on the rule of mixture, the properties of CNTRC are obtained. In this study, only the uniform distributed CNTs are employed through the thickness direction of element. To achieve the natural frequencies and shape modes, the eigenvalue problem is also solved. Using Total Lagrangian Principles, large amplitude free vibration is considered based on the first normalized mode shape of structure. Different well-known plane problem benchmarks and some proposed ones are studied to validate the accuracy and capability of authors' formulations. In addition, the effects of length to the height ratio of beam, CNT's characteristics, support conditions and normalized amplitude parameter on the linear and nonlinear vibration parameters are investigated.