• Transactions of the Korean hydrogen and new energy society
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• v.20 no.6
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• pp.499-504
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• 2009

The effect of gas diffusion layer (GDL) compression caused by different stack clamping pressures on fuel cell performance was experimentally studied in a miniature 5-cell proton exchange membrane fuel cell (PEMFC) stack. Three stacks with different GDL compressions, 15%, 35% and 50%, were prepared using SGL 10BC carbon fiber felt GDL and Gore 57 series MEA. The PEMFC stack performance and the stack stability were enhanced with increasing stack clamping pressure resulting in the best performance and stability for the stack with higher GDL compressions up to 50%. The excellent performance of the stack with high GDL compression was mainly due to the reduced contact resistance between GDL and bipolar plate in the stack, while reduced gas permeability of the excessively compressed GDL in the stack hardly affected the stack performance. The high stack clamping pressure also resulted in excessive GDL compression under the rib areas of bipolar plate and large GDL intrusion into the channels of the plate, which reduced the by-pass flow in the channels and increase gas pressure drop in the stack. It seems that these phenomena in the highly compressed stack enhance the water management in the stack and lead to the high stack stability.

• 한국신재생에너지학회:학술대회논문집
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• 2008.05a
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• pp.1-4
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• 2008

Fuel cells have the potential of providing several times higher energy storage densities than those possible using current state-of-the-art lithium-ion batteries, but current energy density of fuel cell system is not better than that of lithium-ion batteries. To achieve the high energy density, volume and weight of fuel cell system need to be reduced by miniaturizing system components such as stack, fuel tank, and balance-of-plant. In this paper, the thin flexible PCB (Printed circuit board) is used as a current collector to reduce the stack volume. Two end plates are made from light weight aluminum alloy plate. The plate surface is wholly oxidized through the anodizing treatment for electrical insulation. The opening rate of cathode plate hole is optimized through unit cell performance measurement of various opening rates. The performances are measured at room temperature and ambient pressure condition without any repulsive air supply. The active area of MEA is 10.08 $cm^2$ and active area per a unit cell is 1.68 $cm^2$. The peak power density is about 210 mW/$cm^2$ and the air-breathing planar stack of 2 Wis achieved as a small volume of 18 cc.

• Journal of the Korean Electrochemical Society
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• v.6 no.1
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• pp.23-27
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• 2003

In this study investigations have been carried out for the evaluation of small DMFCS under passive operation conditions for use in portable powers. Under passive conditions, a maximum performance was obtained at a methanol concentration of 4 M and at a catalyst loading of $8mg/cm^2$ on both electrodes. By optimizing various parameters, we could achieve the highest performance of $55mW/cm^2$ at 1 attn and at R.T.A monopolar stack consisting of 6 unit cells with active area of $4.5cm^2/cell$ was prepared and it showed a uniform voltage distribution all over the cells and it had a power output of 1 watt and a power density of $37mW/cm^2$ A monopolar stack which consisted of 16 cells and produced a 2.4W power was also fabricated and was tested for operation of a miniature car.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.159-167
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• 2005

Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the $Schr{\ddot{o}}dinger$ and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.